Low temperature glass-to-glass wafer bonding

In this paper, results of successful anodic bonding between glass wafers at low temperature are reported. Prior to bonding, a special technique was used, i.e., an amorphous and hydrogen free silicon film was deposited on one of the glass wafers using a sputtering technique. The effects of bonding temperature and voltage were investigated. The bonding temperature and the voltage applied ranged from 200/spl deg/C to 300/spl deg/C and 200 V to 1000 V, respectively. As the bonding temperature and bonding voltage increased, both the unbonded area and the size of voids decreased. Scanning electron microscope (SEM) observations show that the two glass wafers are tightly bonded. The bond strength is higher than 10 MPa for all the bonding conditions. Furthermore, the bond strength increases with increasing bonding temperature and voltage. The study indicates that high temperature and voltage cause more Na/sup +/ ions to neutralize at the negative electrode, which leads to higher charge density inside the glass wafer. Furthermore, the transition period to the equilibrium state also becomes shorter. It is concluded that the anodic bonding mechanisms involve both oxidation of silicon film and the hydrogen bonding between hydroxyl groups.     

Silicon Nitride Films Deposited by RF Sputtering for Microstructure Fabrication in MEMS

In the present work, we report silicon nitride films deposited by a radio- frequency (RF) sputtering process at relatively low temperatures (<260°C) for microelectromechanical system (MEMS) applications. The films were prepared by RF diode sputtering using a 3-inch-diameter Si₃N₄ target in an argon ambient at 5 mTorr to 20 mTorr pressure and an RF power of 100 W to 300 W. The influence of the film deposition parameters, such as RF power and sputtering pressure, on deposition rate, Si-N bonding, surface roughness, etch rate, and stress in the films was investigated. The films were deposited on single/double-side polished silicon wafers and transparent fused-quartz substrates. To explore the RF-sputtered silicon nitride film as a structural material in MEMS, microcantilever beams of silicon nitride were fabricated by bulk, surface, and surface-bulk micromachining technology. An RF-sputtered phosphosilicate glass film was used as a sacrificial layer with RF-sputtered silicon nitride. Other applications of sputtered silicon nitride films, such as in the local oxidation of silicon (LOCOS) process, were also investigated.     

Wafer bonding for III–V on insulator structures

The InP and GaAs wafers were bonded to GaAs substrates using a siliconnitride intermediate layer. Key process parameters include the silicon-nitride surface roughness and density as determined by atomic-force microscopy and x-ray reflectivity. We demonstrate that silicon nitride can be bonded without any chemical-mechanical polishing step. Silicon-nitride films produced by plasma-enhanced chemical-vapor deposition (PECVD) and deposition by sputtering were compared for bonding compatibility. Smooth silicon-nitride layers (root-mean-square roughness <0.7 nm) were found to produce large areas of bonded material and an oxygen-plasma treatment (200 mtorr, 200 W, 60 s) produced strong nitride/nitride bonding. The strain in the InP layer after transfer to the GaAs substrate was determined using x-ray reciprocal-space mapping (RSM). The crystalline quality of the InP layer was examined with high-resolution x-ray scattering.     

Effective cleaning process and its influence on surface roughness in anodic bonding for semiconductor device packaging

Wafer cleanliness and surface roughness play a paramount role in an anodic bonding process. Impurities and the roughness on the wafer surface result in unbonded areas which lead to fringes and Newton׳s rings. With an augment in surface roughness, lesser area will be in stroke thus making more pressure and voltage to be applied onto the wafers for better bonding. Eventually it became mandatory to choose the best cleaning process for the bonding technology that can substantially reduce the impurities and surface roughness. In this paper, we investigate the bonding of silicon/oxidized silicon on Pyrex (CORNING 7740) glass with respect to surface roughness and cleanliness of the wafers by performing three renowned cleaning processes such as degreasing, piranha, RCA 1& 2 (SC‐Standard Cleaning 1 and 2) and found that RCA compromises the best between the roughness and cleanliness. Studies were also extended to find out the effects of applied voltage and load on the bonded surface. It was observed for samples cleaned with RCA, an increase of 45% in maximum current and decrease of 75% in total bonding time with the applied load and voltage among all the cleaning techniques used. Three dimensional structures for pressure sensor application were successfully bonded by selecting the appropriate load and cleaning process. Atomic force microscopy analysis was done to investigate the surface roughness on silicon/oxidized silicon and Pyrex glass for different cleaning processes. Scanning electron microscopy and optical imaging were performed on the interface for the surface integrity of the bonded samples.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H₂SO₄, 96%) and hydrogen peroxide (H₂O₂, 30%), 120 °C), SC1 (1:1:5 mixture of NH₄OH, H₂O₂ and H₂O, at 80 °C) or HF solution (6 parts of 40% NH₄F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film.     

Influence of tungsten sputtering target density on physical vapor deposition thin film properties

Tungsten (W) is commonly used for diffusion barrier, via, and gate material in semiconductor devices. In order to achieve the desired properties and minimize particle generation, control of the sputter target properties, which include density, purity, grain size, and orientation, are essential. This study focused on the effect of sputtering target density on the thin-film properties and defect generation. By controlling the powder sintering process, three sputtering targets from 82.5% to 99.5% of theoretical density were prepared. By physical vapor deposition (PVD), about 1600 Å thin films were deposited onto the silicon wafers. The deposited films were then evaluated by four-point probe, x-ray diffraction (XRD), and scanning electron microscope (SEM) to determine the influence of target density on the deposited film properties. In addition to film properties, the erosion morphology on the sputtered surface was also investigated by SEM. The voids are known to be the potential particle sources from the target. By monitoring the generation of voids, the correlation between target density and potential particle sources was established.     

Reliability of industrial packaging for microsystems

Packaging concepts for silicon-based micromachined sensors exposed to harsh environments are explored. By exposing the sensors directly to the media and applying protection at the wafer level the packaging and assembly will be simplified as compared to conventional methods of fabrication.Protective coatings of amorphous silicon carbide and tantalum oxide are suitable candidates with etch rates below 0.1 Å/h in aqueous solutions with pH 11 at temperatures up to 140°C. Si-Ta-N films exhibit etch rates around 1 Å/h. Parylene C coatings did not etch but peeled off after extended exposure times at elevated temperatures. The best diamond-like carbon films we tested did not etch, but delaminated due to local penetration of the etchants.Several glue types were investigated for chip mounting of the sensors. Hard epoxies, such as Epotek H77, on the one hand exhibit high bond strength and least degradation and leakage, but on the other hand introduce large sensor output drift with temperature changes. Softening of the Epo-tek H77 was observed at 70°C.An industrially attractive thin-film anodic silicon-to-silicon wafer bonding process was developed. Glass layers are deposited at 20 nm/s (1.2 μm/min) by electron-beam evaporation and bond strengths in excess of 25 N/mm² are obtained for bonding temperatures higher than 300°C.Through-hole electrical feedthroughs with a minimum line width of 20μm and a density of 250 wires per cm were obtained by applying electro-depositable photo-resist. Hermetically sealed feedthroughs were obtained using glass frits, which withstand pressures of 4000 bar.     

Low-Temperature Cu-Cu Bonding Using Silver Nanoparticles Fabricated by Physical Vapor Deposition

Silver nanoparticles (Ag NPs) fabricated by physical vapor deposition (PVD) were introduced in Cu-Cu bonding as surface modification layer. The bonding structure consisted of a Ti adhesive/barrier layer and a Cu substrate layer was fabricated on the silicon wafer. Ag NPs were deposited on the Cu surface by magnetron sputtering in a high-pressure environment and a loose structure with NPs was obtained. Shear tests were performed after bonding, and the influences of PVD pressure, bonding pressure, bonding temperature and annealing time on shear strength were assessed. Cu-Cu bonding with Ag NPs was accomplished at 200°C for 3 min under the pressure of 30 MPa without a post-annealing process, and the average bonding strength of 13.99 MPa was reached. According to cross-sectional observations, a void-free bonding interface with an Ag film thickness of around 20 nm was achieved. These results demonstrated that a reliable low-temperature short-time Cu-Cu bonding was realized by the sintering process of Ag NPs between the bonding pairs, which indicated that this bonding method could be a potential candidate for future ultra-fine pitch 3D integration.     

微机械加工技术

微机械加工技术是发展微型固态集成传感器,微执行器和微机械构件的一种关键技术,它以硅作为基本材料,集合了精密腐蚀、薄膜生长、硅—绝缘体和硅—硅的键合技术、层间连接技术以及其它集成电路的典型工艺去制造各种三维以硅为基础的微机械和微型器件。本文重点介绍微机械加工的几种关键技术和我们的主要研究结果。     

Room temperature wafer bonding of silicon, oxidized silicon, and crystalline quartz

The use of plasma immersion as preparation for room temperature wafer bonding has been investigated. Silicon wafers have been successfully bonded at room temperature after exposure to oxygen or argon plasma. Oxidized silicon wafers and crystalline quartz have been bonded after exposure to oxygen plasma. The bonded interfaces exhibit very high surface energies, comparable to what can be achieved with annealing steps in the range of 600–800°C using normal wet chemical activation before bonding. The high mechanical stability obtained after bonding at room temperature is explained by an increased dynamic in water removal from the bonded interface allowing covalent bonds to be formed. Electrical measurements were used to investigate the usefulness of plasma bonded interfaces for electronic devices.     

The effect of forming gas anneal on the oxygen content in bonded copper layer

Using a combination of copper (Cu) thermocompression bonding and silicon wafer thinning, a face-to-face silicon bi-layer layer stack is fabricated. The oxygen content in the bonded Cu layer is analyzed using secondary ion mass spectrometry (SIMS). Copper-covered wafers that are exposed to the air for 12 h and 12 days prior to bonding exhibit 0.08 at.% and 2.96 at.% of oxygen, respectively. However, prebonding forming gas anneal at 150°C for 15 min on 12-day-old Cu wafers successfully reduces the oxygen content in the bonded Cu layer to 0.52 at.%.     

Wafer bonding of (211) Cd<Subscript>0.96</Subscript>Zn<Subscript>0.04</Subscript>Te on (001) silicon

We have successfully bonded (211) cadmium zinc telluride (CZT) substrates onto (001) Si substrates for subsequent epitaxial-layer deposition of mercury cadmium telluride device layers. Silicon-nitride intermediate layers were employed as they provide both low surface roughness, which is necessary for bonding, and low absorption in the 1–10-μm range. Prior to bonding, the SiN layers were activated using oxygen plasma. Transmission infrared (IR) imaging showed >70% bonded area of a 10 mm×10 mm CdZnTe substrate onto a Si substrate. After the initial bond, the structure was exposed to a low-temperature anneal (150°C) for extended periods of time (22 h) to increase the bond strength. This process was sufficient to produce a CdZnTe on silicon structure that was able to withstand subsequent chemical-mechanical polishing (CMP) of the CZT substrate. We also investigated CMP of the transferred CdZnTe to improve the surface for subsequent epitaxial deposition. A Br/ethylene glycol/methanol solution produced the lowest damage levels, as determined by triple axis x-ray diffraction (TAD) while a standard silica/NaOH treatment produced a surface with <0.5-nm root mean square (RMS) roughness.     

Role of hydrogen in the surface passivation of crystalline silicon by sputtered aluminum oxide

Aluminum oxide films can provide excellent surface passivation on both p‐type and n‐type surfaces of silicon wafers and solar cells. Even though radio frequency magnetron sputtering is capable of depositing aluminum oxide with concentrations of negative charges comparable to some of the other deposition methods, the surface passivation has not been as good. In this paper, we compare the composition and bonding of aluminum oxide deposited by thermal atomic layer deposition and sputtering, and find that the interfacial silicon oxide layer and hydrogen concentration can explain the differences in the surface passivation. Copyright © 2010 John Wiley & Sons, Ltd.     

Si-玻璃阳极键合失效机理研究

在采用Si-玻璃阳极键合技术制备微惯性传感器的过程中,实验发现键合圆片中心区域键合失效。通过对键合机理和工艺过程进行分析,认为湿法腐蚀工艺引入钾离子(K+)污染是造成键合失效的主要原因,也可以对键合失效现象给出合理的解释。改变工艺参数进行了键合对比实验,结果表明,未受K+污染的键合圆片没有发生键合失效现象。提出了解决键合失效问题的两种方案,并首次提出在Si片表面生长氧化层提高失效区键合强度的方法;从理论上分析了增加SiO2介质层的可行性。强度测试结果表明,在SiO2厚度为150nm时,键合剪切强度达到14MPa,验证了方案的可靠性。利用上述方法制备出微加速度传感器敏感结构。     

MOS hydrogen sensors with ultrathin layers of palladium

MOS gas sensors were fabricated on n- and p-type silicon (5-7 Ω. cm) with thermal oxide layers ranging in thickness from 66 to 269 Å. A layer of palladium 30 Å thick was deposited through an evaporation mask. A layer of gold 350 Å thick was deposited over the palladium to provide a continuous electrical contact. Measurements were made of the capacitance at 1 MHz as a function of gasambient and time. The devices showed sensitivity to hydrogen at room temperature. Compared to devices fabricated with 300-Å layers of palladium, the thin film devices showed much faster response and recovery at room temperature and reduced magnitude of response. Devices fabricated on p-type silicon were noticably faster than those fabricated on n-silicon. First-order reaction kinetic fits showed general agreement with the data.     

An effort in planarising microwave plasma CVD grown polycrystalline diamond (PCD) coated 4 in. Si wafers

Large area CVD grown diamond coatings should have very smooth surface in many of its applications, like microwave power transmission windows etc. Combination of mechanical and chemical forces during polishing helps to achieve desired surface roughness of the polycrystalline diamond (PCD) coatings. Authors report the variation of pressure, slurry feeding rate, addition of chemicals and the time of polishing to observe the efficiency of chemo-mechanical polishing (CMP) technique in planarising CVD diamond material grown over 100 mm diameter silicon wafers. PCD were found to be polished by bringing down the as-grown surface roughness from 1.62 µm to 46 nm at some points on large areas. One coherence scanning interferometer was used to check the roughness at different stages of CMP. Raman spectroscopy was used to evaluate the polished PCD samples in terms of their quality, internal stress at different positions on the same wafer surface after CMP process. It was found that the well polished regions were of better quality than the less polished regions on the same wafer surface. But due to coating non-uniformity of the deposited PCD grown by microwave plasma CVD over large area, CMP could not produce uniform surface roughness over the entire 100 mm diameter wafer surface. We concluded that CMP could effectively but differentially polish large area PCD surfaces, and further process improvements were needed.     

Thickness Effect of Nb-Doped TiO<Subscript>2</Subscript> Transparent Conductive Oxide Grown on Glass Substrates Fabricated by RF Sputtering

Transparent conducting Nb-doped titanium oxide (NTO) films were deposited on a non-alkali glass substrate using an RF magnetron sputtering method with post-annealing. Structural, electrical and optical properties of the NTO films were found to be strongly dependent on film thickness. A resistivity of 4.2 × 10^?3 Ω cm and an average visible transmittance of ～70% were obtained at the film thickness of 360 nm, indicating that the polycrystalline NTO fabricated by the sputtering method has sufficient potential as a transparent conducting oxide (TCO) candidate for practical applications.     

Molds and Resists Studies for Nanoimprint Lithography of Electrodes in Low-Voltage Polymer Thin-Film Transistors

A low-cost patterning of electrodes was investigated looking forward to replacing conventional photolithography for the processing of low-operating voltage polymeric thin-film transistors. Hard silicon, etched by sulfur hexafluoride and oxygen gas mixture, and flexible polydimethylsiloxane imprinting molds were studied through atomic force microscopy (AFM) and field emission gun scanning electron microscopy. The higher the concentration of oxygen in reactive ion etching, the lower the etch rate, sidewall angle, and surface roughness. A concentration around 30 % at 100 mTorr, 65 W and 70 sccm was demonstrated as adequate for submicrometric channels, presenting a reduced etch rate of 176 nm/min. Imprinting with positive photoresist AZ1518 was compared to negative SU-8 2002 by optical microscopy and AFM. Conformal results were obtained only with the last resist by hot embossing at 120 °C and 1 kgf/cm² for 2 min, followed by a 10 min post-baking at 100 °C. The patterning procedure was applied to define gold source and drain electrodes on oxide-covered substrates to produce bottom-gate bottom-contact transistors. Poly(3-hexylthiophene) (P3HT) devices were processed on high-κ titanium oxynitride (TiO _x N _y ) deposited by radiofrequency magnetron sputtering over indium tin oxide-covered glass to achieve low-voltage operation. Hole mobility on micrometric imprinted channels may approach amorphous silicon (～0.01 cm²/V s) and, since these devices operated at less than 5 V, they are not only suitable for electronic applications but also as sensors in aqueous media.     

High-quality conformal silicon oxide films prepared by multi-step sputtering PECVD and chemical mechanical polishing

High-quality conformal oxide films were obtained by using multi-step sputtering (MSSP) plasma enhanced chemical vapor deposition (PECVD) process with argon ion sputtering and chemical mechanical polishing (CMP). The repeated deposition by plasma enhanced chemical vapor deposition (PECVD) and anisotropic etching of oxide films by multi-step sputtering PECVD improve the step coverage and gap filling capability significantly. The argon plasma treatment enhances the binding energy of Si-O in the SiO₂ network, and the temperature dependence of stress for MSSP oxide film showed no hysteresis after the heating cycle up to 440 °C. The stress-temperature slope of MSSP oxide film was found to be much less than that of conventional PECVD oxide film. The slope for 1.1 μm thick film is about 5.8×10⁵ dynes/cm²/°C which is smaller than that of thermally grown oxide film. It seems that MSSP oxide film reduces stress-temperature hysteresis and becomes more dense and void-free in the narrow gaps with inter-metal spacing of 0.5 μm. After filling of the narrow gap, we adopted the CMP process for global planarization and obtained good planarization performance. The uniformity of the film thickness was about 4% and the degree of the planarization was over 95% after CMP process.