Self-repairing adder using fault localization

In this paper we propose an area-efficient self-repairing adder that can repair multiple faults and identify the particular faulty full adder. Fault detection and recovery has been carried out using self-checking full adders that can diagnose the fault based on internal functionality, independent of a fault propagated through carry. The idea was motivated by the common design problem of fault propagation due to carry in various approaches by self-checking adders. Such a fault can create problems in detecting the particular faulty full adder, and we need to replace the entire adder when an error is detected. We apply our self-checking full adder to a carry-select adder (CSeA) and show that the resulting self-checking CSeA consumes 15% less area compared to the previously proposed self-checking CSeA approach without fault localization. After observing fault localization with reduced area overhead, we utilize the self-checking full adder in constructing a self-repairing adder. It has been observed that our proposed self-repairing 16-bit adder can handle up to four faults effectively, with an 80% probability of error recovery compared to triple modular redundancy, which can handle only a single fault at a time.     

你的厨房还需要什么

上世纪90年代中国家庭普遍用上了抽油烟机，它解决了中式厨房油烟危害人体健康的问题，因此有人称抽油烟机为中式厨房带了第一次革命。其实厨房里还有一种产品，它同抽油烟机一样重要，就是食物垃圾处理器，它引领了健康厨房的第二次革命。     

The microarchitecture of the synergistic processor for a cell processor

This paper describes an 11 FO4 streaming data processor in the IBM 90-nm SOI-low-k process. The dual-issue, four-way SIMD processor emphasizes achievable performance per area and power. Software controls most aspects of data movement and instruction flow to improve memory system performance and core performance density. The design minimizes instruction latency while providing for fine grain clock control to reduce power.     

Multithreaded processor architectures

The authors describe how independent streams of instructions, interwoven on a single processor, fill its otherwise idle cycles and so boost its performance. They detail how such multithreaded architectures take the tack of hiding latency by supporting multiple concurrent streams of execution. When a long-latency operation occurs in one of the threads, another begins execution. In this way, useful work is performed while the time-consuming operation is completed     

Sampled-data charge processor

A general-purpose analogue signal processor is presented in which all operations are performed in a charge domain. The processor can be customized to each application according to an instruction program. The processor is composed of amplifiers, analogue switches, capacitors and a memory. Charge-domain processing techniques and a calibration technique are used to reduce the requirement for a capacitor precision-ratio. An application to bandpass filtering is demonstrated.     

Array processor supercomputers

The authors describe the range of hardware variations of array processors, a form of SIMD (simple instruction stream, multiple dates stream architecture), comparing and contrasting the significant differences among them and briefly illustrating the wide range of algorithms that can effectively utilize them. Three applications are reviewed. The first application, image convolution, represents the traditional numerically computationally intensive areas of application. SIMD array processors are sufficiently powerful to process digital imagery in real time easily. The second application, an example of real-time database management, is the air traffic control problem. The problem cannot be solved today by networks of computers that are successfully used in similar, less time-critical applications. With an array processor there is sufficient real time remaining after the present system tasks are accomplished to realize additional system enhancements. The third application area, graph algorithms, which is more theoretical, is representative of problems for which the simplicity of the array processor solution results in an execution time better than the best theoretical case for a conventional sequential implementation     

WLAN security processor

A novel wireless local area network (WLAN) security processor is described in this paper. It is designed to offload security encapsulation processing from the host microprocessor in an IEEE 802.11i compliant medium access control layer to a programmable hardware accelerator. The unique design, which comprises dedicated cryptographic instructions and hardware coprocessors, is capable of performing wired equivalent privacy, temporal key integrity protocol, counter mode with cipher block chaining message authentication code protocol, and wireless robust authentication protocol. Existing solutions to wireless security have been implemented on hardware devices and target specific WLAN protocols whereas the programmable security processor proposed in this paper provides support for all WLAN protocols and thus, can offer backwards compatibility as well as future upgrade ability as standards evolve. It provides this additional functionality while still achieving equivalent throughput rates to existing architectures.     

数字信号处理器

本文简述了国内目前应用的第一代数字信号处理器TNTEL 2920,介绍了开始开发的第二代产品TMS32020。     

高速场景网络覆盖断点自修复方法研究

为降低高速公路站点故障对网络质量的影响,本文提出一种高速公路站点故障后基于大数据的网络覆盖自修复的方法,依靠切换链识别技术、替补站点均衡筛选算法和应用黄金分割搜索算法的自动优化方法,实现替补站点的选择和自动优化,保障高速场景用户网络的良好感知。     

Modern central processor architecture

A number of significant architectural concepts which have evolved in recent years are reviewed. These concepts are: the notion of process and the facilities for process management, such as dispatching and synchronization; the use of segmentation in organizing address spaces, and the resulting sharing and protection capabilities; the control of access to data and procedures via multiple privilege levels; the use of automatic stack management for procedure calling; and the structure of logical and physical I/O channels and I/O operations queueing. The rationale for including these concepts in modem central processor architectures, such as in the Honeywell Series 60, is also presented.     

The GIGAswitch control processor

Concerns about guaranteed forward progress and high performance can be addressed in a networking device. Guaranteed progress is provided by proper queuing, buffer quota, and interrupt strategies. High performance is provided by efficient multicast, constant-time address searches, and minimized cache refills from main memory. The GIGAswitch is an extensible, scalable networking platform. It is a bridge connected to many high-speed FDDI LANs, and it can be extended to additional media types through additional types of line cards. Its role in the network can be extended through software upgrades. The GIGAswitch is physically scalable by allowing a few or many line cards to be inserted. This physical scalability leads to effective network bandwidth scalability because crossbar switching technology allows cards to communicate in parallel without contending for a single shared bus. The GIGAswitch crossbar provides a maximum of 34 ports to connect to external networks. Organizations that need to increase their network bandwidth by more than a factor of 34 can use a collection of GIGAswitch systems to do so. The switch control processor is one kind of card that plugs into the GIGAswitch, and it has the special role of specifying to the rest of the box how packets are to be processed. The SCP is a high-performance, general-purpose processing engine     

应用处理器浮出水面

多年来,DSP最擅长的是数字信号处理,分通用与专用.专用满足特定市场的大量需要,如DVD芯片等.现在通用DSP在结构上也不那么单一了,例如,通用DSP中嵌入RISC内核及各种功能、接口,出现了满足数码相机与音频、视频流的流媒体处理器;DSP与MCU融合,诞生了DSC(数字信号控制器),满足电机等既需要实时控制又需要中等速度处理的应用.     

网络处理器与CompactPCI

在目前的市场中，网络处理器（Network Processor）是最专业的处理器之一，这种处理器的目的在于希望能以At Line Rate来处理封包格式的数据。最近几年来，芯片供货商正透过各种WAN edge/access、无线网络基础建设以及网络第4到7层交换机应用等领域中各种特殊应用IC来积极地推广网络处理器。本文将以ATM转换IP的应用为例说明国际PICMG协会制订的规范在网络处理器领域的代表性应用。网络处理器数据的传输接口在标准的CompactPCI平台运用网络处理器时，第一项挑战是如何处理网络处理器的数据传输接口，网络处理器一般是以封包为基本…     

DLP投影机的特点及选用

DLP(Digital Light Processor)投影机是全数字反射式投影机,采用了革新性的投影和显示信息方法,利用美国德州仪器公司开发的数字微反射镜器件DMD~(TM)(Digital Micormirror Device),完成了显示数字可视信息的最终环节,使投影机产品进入了数字时代。     

蓝牙音频信号处理器

蓝牙的关键特性是支持链路和应用领域的音频固有的服务质量。Motorola 的蓝牙系统方案是基于蓝牙固有的音频能力,给出可能的最高质量的音频。给出蓝牙高质量音频的关键器件是蓝牙音频信号处理器(BTASP),BTASP已被设计到MC71000协议控制器中。蓝牙音频信号处理器用于处理蓝牙系统中所有计算密集的音频功能。蓝牙支持用Log-PCM(A-Law或m- Law)或CVSD压缩的语音链路。语音链路是双工,而数据率固定为64Kbit/s。规定四种不同的信息包类型:HV1,HV2,HV3信息包（用10,20或30字节编码音频）和DV信息包(用10字节编码音频和9字节ACL数据…     

Area-efficient FPGA-based FFT processor

A novel architecture for computing the fast Fourier transform on programmable devices is presented. Main results indicate that the use of one CORDIC operator to perform the multiplication by all the 'twiddle factors' sequentially leads to an area saving up to 35% with respect to other cores.     

Memoryless pipelined trigonometric processor

The development and results of memoryless algorithms for the evaluation of sinusoidal functions are described. Differing from the MacLaurin power series method, the algorithms proposed here use the binary representation of an angle in a pipelined manner to calculate sinusoidal functions.<>     

Testing multichip modules

Too complex to be tested as a chip and too packaged to be probed like a board, the multichip module presents a new set of challenges to the test engineer. The author describes how, until dedicated testers are developed, applying board-type tests using an IC tester will prove to be the most effective test methodology     

三模冗余演化自修复系统设计及可靠性分析

将演化硬件与TMR技术相结合在系统级层面设计并实现了一款ETMR系统,并以马尔可夫过程理论为基础探讨了其可靠性规律.发现在任意区间上,ETMR较之单模和TMR系统具有较高可靠性,同时指出修复率与故障率比值是影响ETMR系统可靠度的主要因素,且比值越大其可靠度接近于1的区间跨度越大.系统构建方法及所得结论对于将ETMR系统应用于具体工程实践具有一定的启发和指导作用.     

X模块技术

*小型可插拔10 Gbps转发器的演进轨迹已与力图在这一市场段占支配地位的三种新MSA没有关系。 *两种新的多源协议Xpak和X2很相似,并都借用既有的Xenpak MSA体系结构。 *第三种MSA占用更小的面积,但是将通道设计的许多工作留给你去做。如果你的设计机构有足够的带宽来承担这项额外的角色,则第三种MSA可能是非常经济的。 *Xpak与X2之间的营销之战已经导致出现无确实根据的、可能产生误导的言论。要先证实你听到的言论,再把它融合到你的思想中。