NexFET：一种高可靠与高性能的低压功率DHOSFET

本文介绍一种具有高性能和高可靠性的新型低压功率MOSFET——TI公司的NexFETTM,它将一种高可靠、高性能的RF LDMOSFET与齐纳二极管组合。基于MOSFET结构的RF LDMOSFET将品质因数（Ron＊Qg）改善两倍。一个纵向集成的齐纳二极管钳制峰值开关节点电压的尖峰形成,从而使MOSFET免受击穿。     

TI推出采用新封装工艺的DualCool NexFET功率MOSFET

许多标准架构（PCI、ATCA）、电信及服务器机柜设备都具有固定的支架，机柜尺寸和电源预算，因而当前的主要需求即在不降低效率和性能的情况下提高POL（负载点）的功率密度。为此，TI推出面向高电流DC／DC应用采用全新封装工艺的标准尺寸功率MOSFET产品系列，借助新工艺，可以令功率转换产生的热量能通过对流冷却从封装顶部散出，有效提高了功率密度、电流承受能力，并增强了系统稳定性。     

适合于PSPICE的一种精确的功率MOSFET等效电路

建立了一种新的功率ＭＯＳＦＥＴ等效电路，以便利用先进的电路模拟软件ＰＳＰＩＣＥ对功率ＭＯＳＦＥＴ所有特性进行模拟和分析．对ＩＲ公司的各类ＨＥＸＦＥＴ进行的模拟结果与其数据手册中的实验曲线十分吻合，表明该模型具有较高的精确性．     

一种具有高转换速率的轨对轨运算放大器

为了驱动液晶显示器背板形成不同的灰阶,设计了一种利用齐纳二极管的稳压原理,实现恒定跨导用于TFT-LCD液晶显示的片内运算放大器。采用互补差分输入级,实现了Rail-to-Rail的共模电压输入范围;一种新颖的转换速率增强结构,加快了运算放大器的响应速度;输出级采用Class AB类控制电路,并将其嵌入到求和电路中,以保证较低的噪声和失调。直流增益为101dB,单位增益带宽为13MHz,相位裕度为64°。仿真结果证明该运算放大器工作良好,其面积为500μm×380μm。     

一种采用齐纳管作为开关器件的Dickson电荷泵电路

文章提出了一种基于Dickson原理的电荷泵电路,采用齐纳管作为开关器件。该电路克服了采用MOS管作为开关器件的Dickson电路在多级级联时的转换效率急剧下降问题,并且可以利用齐纳管来稳定输出电压。Spice仿真结果显示,五级齐纳电荷泵可以轻松在3V电源电压下实现10V左右的稳定电压输出。该电路结构简单,与标准CMOS工艺兼容,具有较高的应用价值和经济价值。     

基于CPLD的功率MOSFET保护电路设计与实现

介绍了一种基于CPLD技术的MOSFET器件保护电路的设计与实现。该电路设计方案具有抗干扰能力强、响应速度快和通用性好的优点。通过试验验证了该方案的正确性和可行性。     

TI推出适用Xilinx FPGA的高效电源管理IC TPS75003

目前，德州仪器(TI)宣布推出适用于Xilinx的Spartan-Ⅱ／IIE／3系列现场可编程门阵列(FPGA)的高效电源管理集成电路(IC)TPS75003。     

（英）一种新型低暗计数率单光子雪崩二极管的设计与分析

基于0.18 μm互补金属氧化物半导体(CMOS) 图像传感器工艺提出一种新型的低暗计数率(Dark Count Rate)单光子雪崩二极管(SPAD)器件.该器件是利用P+/LNW(Light N-well doping)结检测光子,并通过低浓度的N型扩散圆形保护环抑制边缘击穿,确保其工作在盖格模式.测试结果表明在室温环境下,直径为8 μm的SPAD器件,雪崩击穿电压为14.2 V,当过调电压设置为2 V时,暗计数率为260 Hz,具有低的暗计数率特性.     

一种新型的高抗干扰高可靠的不停电电源的设计

本文介绍一种新型的不停电电源系统.本电源在工作过程中完全实现自动切换,保证负载始终维持正常工作.当市电停电时,转为直流供电,转换时无电压瞬变.     

一种高可靠低压小体积开关电源的设计

本文介绍了一种高可靠低压小体积开关电源模块的设计思想和设计方法，对变压器的设计以及如何提高效率等关键技术给予了重点介绍。     

A novel low-voltage low-power fully differential voltage and current gained CCII for floating impedance simulations

In this paper we present a new current-mode basic building block that we named voltage and current gained second generation current conveyor (VCG-CCII). The proposed active block allows to control and tune both the CCII current gain and the voltage gain through external control voltages. It has been designed, at transistor level in a standard CMOS technology (AMS 0.35 μm), with a low single supply voltage (2 V), as a fully differential active block. The proposed integrated solution, having both low-voltage (LV) and low-power (LP) characteristics, can be applied with success in suitable IC applications such as floating capacitance multipliers and floating inductance simulators, utilizing a minimum number of active components (one and two, respectively). Simulation results, related to floating impedance simulators, are in good agreement with the theoretical expectations.     

一种用于K波段空间行波管模拟预失真电路的设计方法

空间行波管(TWT)预失真电路小型化、轻量化要求使得电路调试难度变大,迫切需要一种预失真电路精确仿真及设计方法来指导产品设计。该文在分析肖特基二极管等效电路模型基础上选择二极管MA4E2039作为非线性发生器件,并建立了MA4E2039的二极管仿真模型。之后通过分析反射式预失真电路结构,获得了影响电路性能的关键参数,并在元器件和版图联合仿真阶段对这些关键参数进行精确仿真。最后对依据仿真结果进行加工的预失真电路进行测试,发现仿真结果和电路实测结果偏差小于15%,将预失真电路与K波段行波管放大器级联实现在输入回退4 dB时3阶交调达到23.77 dBc,实现了行波管的线性化。可见该方法能够用于指导空间行波管预失真电路设计,帮助提高产品开发周期,对于预失真电路的小型化设计也有重要指导意义。     

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags in conformance with ISO/IEC 18000-3 protocol

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags is presented in this paper. The design of the RF analog front-end and digital control is based on ISO/IEC 18000-3 MODE 1 protocol. This paper mainly focuses on RF analog front-end circuits. In order to supply voltage for the whole tag chip, a high efficiency power management circuit with a rather wide input range is proposed by utilizing 15.5 V high voltage MOS transistors. Furthermore, a high sensitivity, low power consumption 10% ASK demodulator with a subthreshold-mode hysteresis comparator is introduced for reader-to-tag communication. The tag chip is fabricated in 0.18-μm 2-poly 5-metal mixed signal CMOS technology with EEPROM process. An on-chip 1 kb EEPROM is used to support tag identification, data writing and reading. The core size of the analog front-end is only 0.94×0.84 mm² with a power consumption of 0.42 mW. Measured results show that the power management circuit is able to maintain a proper working condition with an input antenna voltage range of 5.82–12.3 V; the maximum voltage conversion ratio of the rectifier reaches 65.92% when the tag antenna voltage is 9.42 V. Moreover, the power consumption of the 10% ASK demodulator is only 690.25 nW.     

A research to high-performance multi-level single-phase AC/DC power factor correct switching converter

This letter studies and analyzes the working features of main circuit of tri-level boost Power Factor Correct （PFC） converter and the advantages of tri-level switch converter in aspects of bearing high-voltage of power components, overall system loss and magnetic component selection based upon the single-level boost PFC switch converter. Besides, relying on the application of microprocessor in power converter technology and DSP （Digital Signal Processing） chip＇s strong calculating capacity, the letter presents the adoption of modified scheme of tri-level boost PFC converter under the control of predictive control algorithm. Moreover, the operating principle and control method are specified, the results of circuit test and analysis are provided and the advantages of predictive control technology-based multi-level boost PFC converter is verified.     

一种基于双通道非线性反馈架构的模拟域功率放大器线性化技术

该文提出一种在模拟域抑制功率放大器(PA)非线性失真的双通道非线性反馈架构,以改善PA线性度,减少邻道泄露。在该架构中,用于抑制非线性的电路包含非线性提取环路和反馈调整环路。非线性提取环路通过耦合器提取PA输入和输出信号,进行幅度和相位对齐后抵消线性信号,保留PA产生的非线性失真。反馈调整环路包含两条独立反馈通道,且信号通过非线性提取环路和反馈调整环路中两条通道分别反馈后的总时延具有两倍关系,使反馈环路呈现2阶Delta-Sigma结构形式,相比于单通道非线性反馈架构具有更好的失真抑制性能。并且通过所提方法配置反馈通道参数,可以实现不同目标频点下非线性失真的灵活抑制。最后设计了一个使用CMPA0060002F商用功放芯片的实验平台,对于带宽为40 MHz,载频为780 MHz的测试信号,在当前6 ns的硬件反馈时延条件下,可以使邻道功率泄露比(ACLR)单边带改善11 dB或双边带改善6 dB,且通过减小反馈时延能够取得更好的性能。     

碳化硅MPS:新一代功率开关二极管

碳化硅MPS(Merged PiN Schottky diode)具有很好的开关特性，并具有PiN二极管高阻断电压、低漏电流和SBD小开启电压，大导通电流以及高开关速度的优点，是最有希望的新一代功率开关二极管。文章系统地介绍了碳化硅MPS的结构和性能。理论和实验分析表明，碳化硅材料的优异性能与MPS结构的优势相结合，是当今功率开关管发展的趋势。     

A novel trench gate floating islands power MOSFET (TG-FLIMOSFET): Two-dimensional simulation study

Novel trench gate floating islands MOSFET (TG-FLIMOSFET) designed using the concept of “Opposite Doped Buried Regions” (ODBR) and floating islands (FLI) along with trench gate technology is proposed and verified using two-dimensional simulations. The conventional FLIMOSFET experimentally demonstrated recently, although offers lowest on-resistance in the low voltage range, however, suffers from quasi-saturation effect like any other power MOSFETs. The proposed TG-FLIMOSFET demonstrated to obtain about 30% reduction in peak electric field in drift region of the proposed device. TG-FLIMOSFET also demonstrates quasi-saturation free forward and transconductance characteristics, improved synchronous rectifying characteristics, identical breakdown voltage, reduced on-resistance and increased transconductance ‘gm’ when compared with the conventional FLIMOSFET for various trench geometries. The proposed device breaks the limit set by the conventional FLIMOSFET approximately by a factor of 10. A possible process flow sequence to fabricate the proposed device commercially by integrating multi-epitaxial process with trench gate technology is also presented.     

A very-high output impedance charge pump for low-voltage low-power PLLs

This article presents the design of a high output compliance, very-high output impedance single-ended charge pump implemented using a new low-voltage current mirror. The output current is sampled and a feedback loop forces it to be equal to the desired reference current. This results in a very-high output impedance over a very wide output voltage range, accurate Up/Down current matching, and low transient glitches. The proposed charge pump was implemented using STMicroelectronics 1-V 90-nm CMOS process. Simulations using Spectre show that the Up/Down output currents remain constant and matched within 1% over a charge pump output voltage ranging from 119 to 873 mV. Monte Carlo process variations and mismatch simulations indicate that the 1-σ standard deviation between the Up and Down current components is , or 6.8% of the nominal charge pump current at either end of the output voltage range.     

一种准优化PAPR编码在OFDM系统中的应用

本文提出了一种较简单的适用于高速率正交频分复用(OFDM)传输系统的准优化峰均功率比(PAPR)编码方案.方案中不仅给出了优良码字的寻找方法,还阐述和证明了峰值包络功率(PEP)不随码字的循环移位和翻转而改变的特性.本文提出的编码算法主要由选择优良码字、码字的循环移位和码字的翻转三部分组成.计算机仿真的结果显示该编码能够获得与最小化编码相似的传输可靠性,但是码率却得到了一定的改善,方法也更简单些.     

一种利用发光光谱估计LED正向电压的方法

提出了一种通过发光光谱估计发光二极管(LED)正向电压的方法。推导了LED正向电压与结温的关系,探讨了利用发光光谱估计结温的方法,从而建立了发光光谱和正向电压的联系。本文方法不需要直接测量结温和理想因子等参数,只由发光光谱就可得到较为准确的LED正向电压值。实验结果表明,正向电压的光谱估计值和实际测量值能够较好的吻合。