基于线性“与或”门的新型超高速数字电路

本文指出了线性“与或”门与发射极功能逻辑的联系，通过理论计算与ＰＳＰＩＣＥ模拟证明了线性“与或”门的极高速工作特性和可多级级联工作能力，在对线性“与或”门所需配用的高速开关分析基础上，设计了两种ＥＣＬ电路，本文还讨论了应用线性“与或”门设计超高速数字电路的准则以及有关的组合和时序电路设计实例。     

中值滤波电路的设计

本文采用我国首创的ＤＹＬ集成线性“与或”门设计成的中值滤波电路，该电路具有结构简单、延时小等优点，可用于实时信号处理。     

多值DYL电路的逻辑设计

本文在前文的基础上具体介绍了MV-DYL电路的各种设计方案。实验证明这些电路工作可靠,性能稳定。本文还根据MV-DYL电路的特点,提出一种高速的多值逻辑“与或”通用阵列,阐明用100个规律排列的MV-DYL“与”门可以实现二元十值逻辑运算功能。     

三值“阈”门和T门集成电路的实现

本文介绍了一种结构简单、适于集成化的三值“阈”门电路,并设计了一个多功能三值T门集成电路。给出了它们的研制结果、逻辑操作波形以及线性“与或”门三值运用时的瞬态特性分析结果。实验表明:我国提出的多元逻辑(DYL)电路结构在实现多值集成电路方面同样有广阔前景。     

极高速多元逻辑电路(DYL)线性“与或”门的研究

本文对多元逻辑电路的主要基本单元线性“与或”门进行了进一步的分析和研究。提出了一种JFET偏置结构,推导了平均传播延迟的分析表达式,建立了晶体管增益与电路参数的关系方程,分析了电路在级联时低电平升高的物理原因。本研究工作采用泡发射极工艺。典型的平均级延迟为0.3ns,功耗延迟积为2.1pJ。实验结果表明,多元逻辑电路是一种有前途的极高速双极型电路。     

一种无隔离区的DYL MOS混合集成新电路

本文实现了一种无隔离区的DYL MOS混合集成的新电路。考虑到多元逻辑电路的主要基本单元线性“与或’门和MOS集成电路的自隔离特点,只要对它的工艺过程稍加调整,即可在同一芯片上制成了互相隔离的适合线性“与或”门需要的大,小β晶体管和P沟道MOS晶体管。用这种集成技术,在N型硅片上试作了由双极晶体管和P沟道MOS晶体管组成的反相单元。这种电路工艺简单,可与DYL线性“与或”门在工艺上兼容,具有输入阻抗高、输出阻抗小,并可和DYL电路与TTL电路相容等优点。     

一种新的高速集成逻辑电路——多元逻辑电路(DYL)

介绍了一种新的高速集成逻辑电路。它不同于常用集成逻辑电路那样基于一种基本单元门电路,而是由几种基本单元组合而成所需的逻辑系统,因而并不要求每种基本单元都有阈值特性。其主要基本单元就是一种高速线性“与或”门,工艺很简单。用较粗尺寸工艺试作的四位全加器进位链样品,实测速度为每级进位上升边延迟1ns,下降边延迟更小。每门最大功耗12.5mw。文中还与几种原有的集成辑逻电路进行了分析比较。     

用加强基础、加强工程的观点,搞好“电子线路”课程的教材建设

“电子线路”是线性电子线路(或低频电子线路)和非线性电子线路(或高频电子线路)的总称。近一年多来,我们对1979年出版的《电子线路》教材进行了全面的修改。目前,线性电子线路的改编工作已完成,非线性电子线路的送审稿也已完成。据初步统计,改编后的教材篇幅较改编前压缩了三分之一。下面我们谈谈在改编过程中的一些想法、请批评指正。“电子线路”是无线电技术类专业的一门主要技术基础课程。对它提出的要求是讲清晶     

多元逻辑12位×12位超高速乘法器

本文以多元逻辑电路(DYL)中的线性与或门为“细胞,构思了体现这种基本门逻辑结构特长的高速数码乘法器结构方案,获得了比目前国际上商品化的高速乘法器更高的运算速度.实验设计制作的 12位× 12位乘法器实测结果表明:最大乘法时间在10ns左右,并能直接插入TTL电路系统使用. 文中分析了DYL线性与或门在二值逻辑系统中的逻辑结构、电路结构特点,提出了用这种基本门构成高速组合逻辑电路的综合方法,并讨论了实现这种基本门阵列高速的关键.     

多元逻辑电路12位高速进位发生器

本文介绍了一种新型结构多元逻辑高速大规模集成电路—DYL12位高速进位发生器(DYL 12-HSCG)。它由DYL的基本单元“线性与或门”构成,具有工艺简单、速度快、工艺容差大、合格率高的特点。文中简要地通过与其它系列电路的先行进位发生器的比较,进而衬托出了DYL的优越性。经过随机逻辑功能测试仪对样品的全功能测试,和把它装入DYL-1300处理机的运算器中运转,证实了这种DYL 12位高速进位发生器工作可靠,性能稳定,速度快。     

THE NEW SUPER-HIGH-SPEED DIGITAL CIRCUIT BASED ON LINEAR AND-OR GATES

The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.     

有源馈电线性与或门的参数设置与PSpice模拟

根据有源馈电线性与或门的电路结构，分析了它的等效模型，设置了诸电路参数，并应用ＰＳｐｉｃｅ４．０２对１０级级联的线性与或门进行了计算机模拟。结果表明，每级有源馈电线性与或门的平均传输延迟约为０．４ｎｓ，平均逻辑摆幅衰减约为０．０５Ｖ，这证明了它具有超高速及可多级级联的工作特性。     

基于DNA链置换的三级联组合分子逻辑电路设计

DNA计算研究内容繁多复杂,DNA复杂逻辑电路的搭建属于DNA计算的一个重要研究分支,其中逻辑门的构建属于DNA复杂逻辑电路搭建的基础研究,设计出更为简单的逻辑门可以为研究者搭建复杂电路提供参考,节省基础研究的宝贵时间。针对上述问题,该文利用使能控制端思想,采用DNA链置换技术,设计了与或、与非或非和异或同或3种DNA组合逻辑门。结果显示,设计的3种组合逻辑门可实现6种逻辑运算功能,并利用所构建的组合逻辑门成功构造了多级联组合分子逻辑电路,为DNA计算提供了更多的解决方案,促进了DNA计算机的发展。     

The effect of logic block architecture on FPGA performance

This authors explore the effect of logic block architecture on the speed of a field-programmable gate array (FPGA). Four classes of logic block architecture are investigated: NAND gates, multiplexer configurations, lookup tables, and wide-input AND-OR gates. An experimental approach is taken, in which each of a set of benchmark logic circuits is synthesized into FPGAs that use different logic blocks. The speed of the resulting FPGA implementations using each logic block is measured. While the results depend on the delay of the programmable routing, experiments indicate that five- and six-input lookup tables and certain multiplexer configurations produce the lowest total delay over realistic values of routing delay. The fine grain blocks, such as the two-input NAND gate, exhibit poor performance because these gates require many levels of logic block to implement the circuits and hence require a large routing delay     

Current hogging logic (CHL)-a new bipolar logic for LSI

Logic functions of current hogging logic (CHL) are established by switching the lateral injection current in intermediate collector p-n-p structures. High functional density is achieved, since NOR, NAND, and complex gates can readily be realized and all logic elements can be placed within a common isolation region. CHL is fabricated with a standard buried collector process, and hence is compatible with linear bipolar circuits and other bipolar logic families. Current levels are employed as the logical variables, and the transfer characteristics of an AND-NOR gate are discussed. CHL offers high static and dynamic noise immunity. The paper demonstrates a static frequency divider as an example of an CHL circuit.     

Design and performance of multistage GaAs dynamic logic

GaAs Two-Phase Dynamic FET Logic (TDFL) circuits are capable of extremely low power dissipation (20 nW/MHz/gate), high speed (1 GHz), and are compatible with static GaAs logic families. This paper demonstrates that TDFL can be modified to execute two or three stages of logic in one clock phase. This extension provides extremely high functional complexity per gate that can be used to reduce power dissipation, reduce latency, and increase circuit density in both sequential and computationally-oriented applications. The performance of these gates was demonstrated by E/D MESFET IC test circuits fabricated by a digital IC foundry. A one clock cycle, 8-b carry-lookahead adder operated at 350 MHz with only 1.1 mW of power dissipation     

Logic decomposition of speed-independent circuits

Logic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional correctness of a circuit but also speed independence, i.e., hazard freedom under unbounded gate delays. This paper presents a new method for logic decomposition of speed-independent circuits that solves the problem in two major steps: (1) logic decomposition of complex gates and (2) insertion of new signals that preserve hazard freedom. The method is shown to be more general than previous approaches and its effectiveness is evaluated by experiments on a set of benchmarks     

量子逻辑电路故障检测定位及自修复方法研究

针对量子逻辑电路规模逐渐增大,电路可靠性逐渐下降的问题,提出基于单个量子逻辑门在线故障检测定位方法,该方法使用新构造的检测信号生成门与故障检测门,利用奇偶保持特性判断待测量子逻辑门是否发生故障,同时在设计过程中对信号检测电路进行检验,保证检测电路的正确性。此外提出了基于硬件冗余的量子逻辑电路自修复设计方法。实验结果表明,文中故障检测方法在量子门和垃圾位等性能指标上相对已有方法均有了改进,首次实现的量子逻辑电路的自修复设计大大提高了电路的容错能力和可靠性。     

Novel pipeline architectures based on Negative Differential Resistance devices

Devices exhibiting Negative Differential Resistance (NDR) in their I–V characteristic are attractive from the design point of view and circuits exploiting it have been reported showing advantages in terms of performance and/or cost. In particular, logic circuits based on the monostable to bistable operating principle can be built from the operation of two series connected NDR devices with a clocked bias. Monostable to Bistable Logic Element (MOBILE) gates allow compact implementation of complex logic function like threshold gates and are very suitable for the implementation of latch-free fine grained pipelines. This pipelining relies on the self-latching feature of MOBILE operation. Conventionally, MOBILE gates are operated in a gate level pipelined fashion using a four-phase overlapped clock scheme. However other simpler, and higher through-output interconnection schemes are possible. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. Both the proposed architectures are analyzed and experimentally validated. The fabricated circuits use a well-known transistor NDR circuit (MOS-NDR) and an efficient MOBILE gate topology built on its basis. Both solutions are compared and their distinctive characteristics with respect to domino based solutions are pointed out.     

线性最近邻量子电路状态分析及最优逻辑综合

综合量子电路时必须考虑量子电路实现时的约束与限制.某些量子技术中只允许物理上相邻的量子比特有相互作用,实现时必须采用线性最近邻架构.通常通过添加交换门使任意一个量子门的控制位与目标位相近邻,并保证电路的功能不受影响.在分析电路中量子比特状态的基础上,提出了一种新的线性最近邻量子电路构造方法.结果表明:对于所有40320个三比特量子电路,提出方案比已有方案的量子代价优化了约30％.