Reliability of in-situ rapid thermal gate dielectrics in deepsubmicrometer MOSFET's

Several in-situ, rapid thermal gate dielectrics, 6.5-nm thick, including RTO, RTCVD, and RPECVD were used to fabricate fully implanted 0.25-μm NMOSFET's along with Furnace gate oxides. The device reliability was studied by both channel hot-carrier stress and Fowler-Nordheim electron injection. It was found that devices having RTO or RTCVD oxides have about the same hot-carrier resistance as Furnace ones, while RPECVD oxides, deposited directly on Si without a grown oxide interface, were more susceptible to shifts. Both RTCVD and RPECVD oxides have a lower Si-SiO₂ barrier height (2.7 eV); nevertheless, RTCVD oxides show enhanced resistance against interface-state generation, threshold voltage shifts, and charging during Fowler-Nordheim stressing     

New hot-carrier degradation mode in PMOSFETs with W gate electrodes

Hot-carrier degradation of W gate PMOSFETs, which are surface-channel devices because of the work function of W, has been investigated in comparison with polycide (WSi_x/n⁺ poly-Si) ones. In W gate PMOSFETs, transconductance g_m and threshold voltage V_th decrease on the drain avalanche hot-carrier (DAHC) stress, and Δg_m /g_m0 and ΔV_th become minimum at V_G≅V_D/2. By using the charge-pumping technique, it is found that, after stressing at the same stress condition, the interface state density of W gate devices is about 10 times larger than that of polycide ones but the densities of trapped electrons are almost equal. These results indicate that the difference of hot-carrier degradation between W and polycide gate devices is mainly caused by the difference of the interface state density     

Hot-carrier-induced degradation in reoxidized-nitrided-oxiden-MOSFETs under mixed AC-DC stressing

Reduced degradation rate can be observed for reoxidized-nitrided-oxide (RNO) n-MOSFETs under dynamic stressing versus the corresponding static stressing. A new degradation mechanism is proposed in which trapped holes in gate oxide are neutralized by the hot-electron injection, with no significant generation of interface states because of the hardening on the Si-SiO₂ interface by nitridation/reoxidation steps. The RNO device degradation during AC stressing arises mainly from the charge trapping in the gate oxide rather than the generation of interface states. Moreover, the AC-stressed RNO devices are significantly inferior to the fresh RNO devices in terms of DC stressing, possibly due to lots of neutral electron traps in the gate oxide resulting from the AC stressing     

The generation and characterization of electron and hole trapscreated by hole injection during low gate voltage hot-carrier stressingof n-MOS transistors

Hot-carrier stressing carried out on conventional and MDD n-MOS transistors under low gate voltage conditions (V_g⩽V_d/4) is discussed. Following the stress, the devices were subjected to short alternate phases of electron and hole injection into the oxide in order to identify the damage species generated. It is shown that the damage created consists principally of hole and electron oxide traps. This is confirmed using the charge pumping technique. Maximum damage is obtained for conditions of maximum hole injection, indicating that hot holes are responsible for both types of defects. Comparison with maximum interface state damage shows that degradation due to electron traps can be significantly greater than interface state creation in the stressing of n-MOS devices at high drain voltages. The damage is shown to be localized. Two-dimensional simulation of localized charge placed close to the drain junction suggests that equal quantities of positive and negative charge might be created by this stressing. Measurements of capture cross sections for electron trapping reveal two cross sections, σ(1)≈3×10^-15 and σ(2)≈3×10^-16 cm²     

Mechanisms for hot-carrier-induced degradation inreoxidized-nitrided-oxide n-MOSFET's under combined AC/DC stressing

Hot-carrier-induced degradation behavior of reoxidized-nitrided-oxide (RNO) n-MOSFETs under combined AC/DC stressing was extensively studied and compared with conventional-oxide (OX) MOSFETs. A degradation mechanism is proposed in which trapped holes in stressed gate oxide are neutralized by an ensuing hot-electron injection, leaving lots of neutral electron traps in the gate oxide, with no significant generation of interface states. The degradation behavior of threshold voltage, subthreshold gate-voltage swing, and charge-pumping current during a series of AC/DC stressing supports this proposed mechanism. RNO device degradation during AC stressing arises mainly from the charge trapping in gate oxide rather than the generation of interface states due to the hardening of the Si-SiO₂ interface by nitridation/reoxidation steps     

Low-frequency noise characterization of latent damage in thinoxides subjected to high-field impulse stressing

Latent damage in thin oxides, caused by high-field impulse stressing, can lead to increased trap generation in the device during the subsequent hot-carrier stressing. Monitoring of such damage is typically carried out by detecting the change in an appropriate electrical parameter of the device or by extracting the generated interface states and trapped charges. It was found that low-frequency noise measurements could provide a more sensitive alternative for characterizing the electrostatic discharge stress-induced latent damage in thin oxides     

Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device     

AC hot-carrier effects in MOSFETs with furnaceN2O-nitrided gate oxides

AC hot-carrier effects in n-MOSFETs with thin (~85 Å) N₂O-nitrided gate oxides have been studied and compared with control devices with gate oxides grown in O₂. Results show that furnace N₂O-nitrided oxide devices exhibit significantly reduced AC-stress-induced degradation. In addition, they show weaker dependences of device degradation on applied gate pulse frequency and pulse width. Results suggest that the improved AC-hot-carrier immunity of the N₂O-nitrided oxide device may be due to the significantly suppressed interface state generation and neutral electron trap generation during stressing     

Direct lateral profiling of hot-carrier-induced oxide charge andinterface traps in thin gate MOSFET's

A simple charge pumping method has been developed to measure the localized hot-carrier damage in scaled thin-gate MOSFET's. Lateral distributions of both interface traps and oxide charge can be derived directly from experimental charge pumping results without numerical simulation. By the use of this method, we have studied the erase-induced hot-carrier damage in flash EPROM devices, including the lateral distributions of both oxide charge (trapped holes) and interface traps. We discovered the following: the damage is confined within the source diffusion region with a rather wide distribution; the erase-induced oxide charge density is orders of magnitude more than erase-induced interface traps; both the peak density and width of the damage depend strongly on the junction bias during the erase operation. These results should be very useful for the reliability modeling and future device design of flash EPROM's     

反应离子刻蚀铝中nMOS 器件的等离子充电损伤

介绍在等离子工艺中的等离子充电损伤,并且利用相应的反应离子刻蚀(RIE)Al的工艺试验来研究在nMOSFET器件中的性能退化。通过分析天线比(AR)从100:1到10000:1的nMOSFET器件的栅隧穿漏电流,阈值Vt漂移,亚阈值特性来研究由Al刻蚀工艺导致的损伤。试验结果表明在阈值Vt漂移中没有发现与天线尺寸相关的损伤,而在栅隧穿漏电流和低源漏电场下亚阈值特性中发现了不同天线比的nMOS器件有相应的等离子充电损伤。在现有的理解上对在RIEAl中nMOS器件等离子充电损伤进行了讨论,并且基于这次试验结果对减小等离子损伤提出了一些建议。     

Monitoring trapped charge generation for gate oxide under stress[MOS capacitors]

A measurement method to extract the respective quantities and centroids of positive and negative trapped charges, i.e., Q_p and Q_n, generated by the negative current stress for gate oxides is proposed and demonstrated. The method is based on neutralization of and by a low positive current stress to differentiate the effects of Q_p and Q_n. From the extracted quantities and centroids of Q_p and Q_n of negatively stressed oxides, it was found that Q_p and Q_n are generated near the oxide/substrate interface and Q_p is initially much larger than Q_n. After the continuous stressing, Q_p saturates and moves closer to the interface, but Q_n keeps increasing and moves away from the interface, especially for those oxides after the post-poly anneal (PPA) treatment. Q_p is very unstable and easily neutralized, either by a small stress of opposite polarity or the same polarity. For the latter, Q_p is mainly dependent on the level of the final stressing field     

Hole injection enhanced hot-carrier degradation in PMOSFETs used for systems on chip applications with 6.5–2 nm thick gate-oxides

Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide (T_ox=2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above −1.8 V. Devices with T_ox=6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging–discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.     

Distribution of trapped charges in SiO2 film of ap+-gate PMOS structure

To investigate the highly boron-doped SiO₂ film, p⁺ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n⁺-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO₂ interface and electrons accumulate near the polysilicon/SiO₂ interface in p⁺-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p⁺ gate's stress time dependence of I_sub is smaller than that of the n⁺ gate, and the electric field near the drain in the p⁺ -gate PMOSFET was found to be more severe than that of the n⁺ -gate device. The subthreshold slope of the p⁺-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n⁺-gated device did not significantly change. The actual change of V_th was larger than the value derived from Δ_gm using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO₂ film, which assumes the existence of trapped holes in the p⁺-gate PMOSFET, is proposed to explain these phenomena     

Interface trap generation by FN injection under dynamic oxide fieldstress

Interface trap generation under dynamic (bipolar and unipolar) and dc oxide field stress has been investigated with the charge pumping technique. It is observed that regardless of stress type, whether dc or dynamic (bipolar or unipolar), and the polarity of stress voltage, interface trap generation starts to occur at the voltage at which Fowler-Nordheim (FN) tunneling through the oxide starts to build up. For positive voltage, interface trap generation is attributed to the recombination of trapped holes with electrons and to the bond breaking by the hydrogen (H and H⁺) released during stressing. For negative voltage, in addition to these two mechanisms, the bond breaking by energetic electrons may also contribute to interface trap generation. The frequency dependence of interface trap generation is also investigated. Interface trap generation is independent of stressing frequency for unipolar stress but it shows a frequency dependence for bipolar stress     

Characterization of oxide trap and interface trap creation duringhot-carrier stressing of n-MOS transistors using the floating-gatetechnique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I_g-V_g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I_g- V_g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I_g-V _g measurements     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

Investigation of the threshold voltage turn-around effect in long-channel n-MOSFETs due to hot-carrier stress

In this paper, we have investigated the turn-around effect of the threshold voltage (V_th) shift in the case of an n-type long channel MOSFET during hot-carrier stress. This effect is explained by the interplay between interface states and oxide traps, i.e. by the partial compensation of the rapidly created oxide charges by the more slowly created interface states. Significant hole trapping is observed from the negative shift of the threshold voltage during the first seconds of stress. Afterwards, V_th has switched to the positive voltage direction due to the negative charging of interface traps after relatively long stress time. To analyze this phenomenon in detail, a refined extraction technique for the defect distribution from charge-pumping measurements has been employed. Additionally, the obtained results have been explained by our physics-based model of hot-carrier degradation which considers not only channel electrons but also secondary holes generated by impact ionization. In spite of the small hole contribution (compared to that of electrons) to the total defect creation, its impact on the threshold voltage shift is comparable with the electronic one. The reason behind this trend is that hole-induced traps are shifted towards the source, thereby more severely affecting the device behavior.     

Dynamic stress experiments for understanding hot-carrierdegradation phenomena

The results of inhomogeneous hot-carrier injection experiments in which static and dynamic stresses are applied to n-MOSFETs are presented. A qualitative model in which holes play a key role for the final formation of interface states is developed. The holes are injected and trapped within the strained oxide region. The hole-injection process is controlled by hole traps in the oxide, close to the interface. With this model, a large number of dynamic and static hot-carrier stress experiments are consistently explained. Finally, a simple method by which the lifetime of a device under real operation can be predicted from dynamic stress experiments is given     

Characterizing Fluorine-Ion Implant Effects on Poly-Si Thin-Film Transistors With ${hbox{Pr}}_{2}{hbox{O}}_{3}$ Gate Dielectric

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k Pr₂O₃ as gate dielectric is investigated for the first time. Using the Pr₂O₃ gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr₂O₃/poly-Si interface to improve the device electrical properties. The Pr₂O₃ TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr₂O₃ TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr₂O₃ TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr₂O₃ TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.     

A new approach for characterizing structure-dependent hot-carriereffects in drain-engineered MOSFET's

In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N_it ) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N_it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N_it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices