High-speed divider using GaAs ECL/CML gate array

An ECL/CML gate array using GaAs/AlGaAs heterojunction bipolar transistors is reported for the first time. The gate array has up to 12 programmable inputs and outputs. A divide-by-eight circuit configured on this array has been clocked at 3.1 GHz.<>     

Analysis and optimization of BiCMOS gate circuits

A comprehensive view of an optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed. BiCMOS gate delay, when optimized, is found to be expressed as A+B√F, where F is fanout and A and B are coefficients. Since the coefficients can be extracted by SPICE simulation, the delay prediction can be precise, while keeping the delay formula simple enough for circuit designers to derive useful expressions. A procedure for optimizing BiCMOS gates is studied. BiCMOS gate delay can be calculated quickly and optimized efficiently just by looking up a design table which is obtained from SPICE simulations. The procedure for making the design table is technology-independent. Once obtained, the design table can be applied to any design with the same device technology. A sizing strategy of cascaded BiCMOS buffers is derived from the simple delay model. In a 0.8 μm, 9 GHz, BiCMOS process, a BiCMOS-BiCMOS cascaded buffer is optimized when the scale-up factor between two consecutive stages is e ^2.3(≈10.0). A BiCMOS-CMOS cascaded buffer becomes the fastest when the scale-up factor, e^1.6(≈5.0), is employed. The optimization procedure and the sizing strategy can be used for several variants of the basic BiCMOS gate, because the delay model is based on basic circuit models for the variants     

THE QUATERNARY INTERFACE TECHNIQUE IN ECL INTEGRATED CIRCUITS

The theory of differential current switches which applies to the design of multivaluedECL circuits is introduced.In this theory,the switching state of differential transistor pairand signal in ECL circuits are described by switching variables and quaternary signal variables,respectively.he connection operations between the two kinds of variables are introduced todescribe the action process between switching element and signal in the circuits.Based on thistheory,two kinds of interface circuits-2-4 encoder and 4-2 decoder are designed.The computersimulation for the designed circuits by using SPICE program confirms that both circuits havecorrect logic functions,desired DO transfer characteristics and transient characteristics.Theseinterface circuits are compatible with binary circuits in the integrated process,the power supplyequipment,the logic stage and the transient characteristic.Therefore,they can be used as input-output interface of the existing binary ECL integrated circuits so as to decrease the number ofpins of a chip and the connections between chips.     

An analytical model for the determination of the transient responseof CML and ECL gates

In the analysis, the full-range transient response of the gate is calculated using closed-form analytical expressions. This is achieved by generalizing and improving the method used by J.M.C. Stork (IEDM Tech. Dig., p.550, 1988) for the determination of the propagation delay. The proposed model is applicable at low-level injection, unity fan-in, and unity fan-out. The delays related to the transit time, the load, and the junction capacitances are considered. For ECL gates, the emitter follower delay is also included. Various delays (risetime, propagation delay, etc.) calculated using the proposed model agree perfectly with the results of SPICE computer simulations and with the reported experimental values     

三维集成电路中TSV-TSV的耦合分析与优化

TSV-TSV耦合会对三维集成电路的性能造成影响,主要的负面效应就是引入了耦合噪声。为了能够在初期设计阶段准确的估计TSV间的耦合强度,本文首先提出了存在于TSV间的基于二端口网络的阻抗级耦合通道模型,然后推导出了TSV间的耦合强度公式用来描述TSV-TSV耦合效应。通过与三维全波仿真结果的对比,公式的准确度得到了验证。另外,本文提出了一种减小TSV间耦合强度的设计方法。通过SPICE仿真,所提出设计方法不仅可以应用在简单TSV-TSV的电路结构中,还可以应用在含有多个TSV的复杂电路结构中,从而体现了所提出设计方法的可行性,并且为设计者提供了改善三维集成电路电学性能的可能性。     

Analysis and optimization of nanometer CMOS circuits for soft-error tolerance

Nanometer circuits are becoming increasingly susceptible to soft errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper presents a tool for accurate soft-error tolerance analysis of nanometer circuits (ASERTA) that can be used to estimate the soft-error tolerance of nanometer combinational circuits. The tolerance estimates generated by the tool match SPICE-generated estimates closely while taking orders of magnitude less computation time. The second part of the paper presents a tool for soft-error tolerance optimization of nanometer circuits (SERTOPT), which uses the tolerance estimates generated by ASERTA. The number of errors propagated to the primary outputs (POs) is minimized by adding optimal amounts of capacitive loading to the POs of the logic circuit. Using a novel delay-assignment-variation-based optimization methodology, the sizes, supply voltages, and threshold voltages of internal gates (not primary outputs) are chosen to minimize the energy and delay overhead due to the added capacitive loads. Experiments on ISCAS'85 benchmarks show that 79.3% soft-error reduction can be obtained on the average with modest increase in circuit delay and energy. Comparison with other techniques shows that our approach has a significantly better energy-delay-reliability tradeoff compared with others.     

A speed, power, and supply noise evaluation of ECL driver circuits

We present an emitter coupled logic (ECL) active pull-down (APD) circuit which can provide a 10:1 ratio between active and inactive currents. The new APD circuit is compensated for variations in supply and temperature via a clamp voltage. The proposed circuit is evaluated by comparing its performance (in terms of speed, power dissipation, and generated supply noise) with the performance of five other driver circuits     

A synthesis methodology for ECL circuits based on mixed voltage-current representation

This paper presents a synthesis methodology for ECL circuits based on a mixed voltage-current signal representation and operation defined on the voltage and current signals. The ideas presented in this paper are then demonstrated on the design of an BCL 1-bit full adder. The paper concludes by presenting an algebraic system which is suitable for current signal representation and operation on currents.     

On the scaling property of trench isolation capacitance foradvanced high-performance ECL circuits

A detailed study on the scaling property of trench isolation capacitance for advanced high-performance bipolar applications is presented. It is shown that the trench isolation capacitance depends on the trench structure, particularly the trench bottom and the trench fill. The dependence of the trench isolation capacitance on the trench width is analyzed for various commonly used trench structures. The impact on scaled-down high-performance emitter-coupled logic (ECL) circuits is presented     

Theory of differential current switches and logic design of ternary ECL circuits at switch level

Starting from the viewpoint that the switch states and signal values in a digital circuit should be described separately by two different kinds of variable, the interaction between the switching element and signal in multi-valued ECL circuits is analysed and two types of connection operations, threshold switching operation and current switching operation, are proposed. The properties and circuit realizations of these new operations are discussed and the theory of differential current switches applicable to ECL circuits is established. Examples of basic ternary ECL circuits confirm that this theory can effectively guide the logic design of ternary ECL circuits at switch level. The circuits are verified by using the SPICE II program. They have the same logic level difference and transient characteristic as binary ECL circuits. Since the multi-valued ECL circuit uses only one set of power supply and can set several threshold values by using reference levels, it can be fabricated using conventional ECL techniques and is compatible with binary ECL circuits.     

Yield optimization of integrated circuits

A design approach is presented that optimizes the component areas of integrated circuits so as to maximize the yield. The performance index to be optimized is defined as the chip yield divided by the chip area, which corresponds to the number of good chips in a wafer. The area of each component is determined to maximize this performance index by a nonlinear programming technique. The design of integrated circuits with respect to the yield may be mostly narrowed down to the determination of component areas, since the process parameters cannot be adjusted individually for each circuit component. This design approach is described in more detail for the kinds of components whose surface areas cannot be uniquely determined by their nominal parameter values. As a demonstration, the width of a diffused resistor in bipolar integrated circuits was optimized for some example circuits. Some useful results have been obtained for the design of circuit patterns.     

Automated design optimization of integrated switching circuits

A computer program for the optimization of switching circuits with practical design constraints such as limits and interdependencies of circuit parameter values has been developed. The approach implements a fast nonlinear analysis program and a Fletcher-Powell minimization algorithm. An effective parameter perturbation scheme approximates the gradient of the performance index. The use of parameter transformation to handle practical limits on circuit parameters, and penalty functions to incorporate such design constraints as limits on power dissipation, node voltages, and transistor area is described. The optimization of a bipolar decoder and a 3-transistor MOS memory cell are presented as examples.     

Space-mapping optimization of microwave circuits exploitingsurrogate models

A powerful new space-mapping (SM) optimization algorithm is presented in this paper. It draws upon recent developments in both surrogate model-based optimization and modeling of microwave devices, SM optimization is formulated as a general optimization problem of a surrogate model. This model is a convex combination of a mapped coarse model and a linearized fine model. It exploits, in a novel way, a linear frequency-sensitive mapping. During the optimization iterates, the coarse and fine models are simulated at different sets of frequencies. This approach is shown to be especially powerful if a significant response shift exists. The algorithm is illustrated through the design of a capacitively loaded 10:1 impedance transformer and a double-folded stub filter. A high-temperature superconducting filter is also designed using decoupled frequency and SMs     

反馈式ECL记忆门的记忆性能和移位计数器

经过数学论证表明,改进反馈式ECL(MFECL)门可在二个状态中任一态保持稳定,所以认为MFECL门就是一种ECL记忆门或D锁存器.提出了一种由两个ECL记忆门组成的ECL主从D触发器.在上述理论基础上,利用此主从D触发器设计出5进制移位型计数器.经过计算机模拟上述电路,验证了理论和电路的正确性.     

Nonlinear yield analysis and optimization of monolithic microwaveintegrated circuits

In this paper, a discussion about nonlinear yield evaluation and nonlinear yield optimization of MMIC circuits using a physics-based nonlinear lumped-element MESFET model is presented. The lumped elements of the MESFET model are directly calculated by closed expressions related to process parameters. One of the main features of the model is the easy and effective implementation in commercial CAD tools. It allows the use of nonlinear yield algorithms assuming, as statistical variables, the parameters of the technological process, such as: doping density, gate channel length, etc., maintaining at the same time, the advantages of lumped-element MESFET model, in particular fast computation and reduction of convergence problems in harmonic balance for complex circuit topologies     

Design and optimization of dual-threshold circuits for low-voltagelow-power applications

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively     

基于离散三值粒子群算法的MPRM电路面积优化

Having the advantage of simplicity,robustness and low computational costs,the particle swarm optimization (PSO) algorithm is a powerful evolutionary computation tool for synthesis and optimization of ReedMuller logic based circuits.Exploring discrete PSO and probabilistic transition rules,the discrete ternary particle swarm optimization(DTPSO) is proposed for mixed polarity Reed-Muller(MPRM) circuits.According to the characteristics of mixed polarity OR/XNOR expression,a tabular technique is improved,and it is applied in the polarity conversion of MPRM functions.DTPSO is introduced to search the best polarity for an area of MPRM circuits by building parameter mapping relationships between particles and polarities.The computational results show that the proposed DTPSO outperforms the reported method using maxterm conversion starting from POS Boolean functions.The average saving in the number of terms is about 11.5%;the algorithm is quite efficient in terms of CPU time and achieves 12.2%improvement on average.     

反馈式ECL记忆门的记忆性能和移位计数器

经过数学论证表明,改进反馈式ECL(MFECL)门可在二个状态中任一态保持稳定,所以认为MFECL门就是一种ECL记忆门或D锁存器.提出了一种由两个ECL记忆门组成的ECL主从D触发器.在上述理论基础上,利用此主从D触发器设计出5进制移位型计数器.经过计算机模拟上述电路,验证了理论和电路的正确性.     

FAST gradient based yield optimization of nonlinear circuits

Yield optimization of nonlinear microwave circuits operating in the steady state under large-signal periodic excitations is studied. Two novel high-speed methods of gradient calculation, the integrated gradient approximation technique (IGAT) and the feasible adjoint sensitivity technique (FAST) are introduced. IGAT utilizes the Broyden formula with special iterations of Powell to update the approximate gradients. FAST combines the efficiency and accuracy of the adjoint sensitivity technique with the simplicity of the perturbation technique. IGAT and FAST are compared with the simple perturbation approximate sensitivity technique (PAST) on the one extreme and the theoretical exact adjoint sensitivity technique (EAST) on the other. A FET frequency doubler example treats statistics of both linear elements and nonlinear device parameters. This design has six optimizable variables, including input power and bias conditions, and 34 statistical parameters. Using either IGAT or FAST, yield is driven from 40% to 70%. FAST exhibits superior efficiency