Impact of poly-gate depletion on MOS RF linearity

The distortion behavior for thin oxide MOS transistors can be degraded due to polysilicon-gate depletion effects. The nonlinear, bias-dependent gate capacitance for thin oxide MOSFET's results in significant 2nd-order derivatives in gate capacitance, (/spl part//sup 2/C(V/sub gs/)//spl part/V/sub gs//sup 2/), which in turn results in substantial 3rd-order derivative contributions to drain current, (/spl part//sup 3/I/sub ds///spl part/V/sub gs//sup 3/). This may restrict the use of very-thin oxide MOSFET's in RF applications.     

RF performance degradation in nMOS transistors due to hot carriereffects

This paper reports the hot electron induced RF performance degradation in multifinger gate nMOS transistors within the general framework of the degradation mechanism. The RF performance degradation of hot-carrier stressed nMOS transistors can be explained by the transconductance degradation, which resulted from the interface state generation. It has been found that the RF performance degradation, especially minimum noise figure degradation, is more significant than dc performance degradation. From the experimental correlation between RF and dc performance degradation, RF performance degradation can be predicted just by the measurement of dc performance degradation or the initial substrate current. From our experimental results, hot electron induced RF performance degradation should be taken into consideration in the design of the CMOS RF integrated circuits     

Impact of Al composition on RF noise figure of AlGaAs/GaAsheterojunction bipolar transistors

The influence of Al content on the RF noise characteristics of Al _xGa_1-xAs/GaAs heterojunction bipolar transistors (HBT's) is presented. It is shown that the minimum noise figure (F_min) at 2 GHz is reduced by increasing the Al mole fraction (x). This observed improvement in noise figure is directly correlated to the differences in dc current gain. The lowest measured F_min(2 GHz) of HBT's with emitter dimensions 2×(3.5×30) μm², were 1.3, 1.61, and 2.1 dB for x=0.35, 0.30, and 0.25 devices, respectively at I_c=3 mA. The measured results were found to agree well with calculated values over a wide range of collector currents     

Impact of downscaling on high-frequency noise performance of bulk and SOI MOSFETs

Parameters limiting the improvement of high-frequency noise characteristics for deep-submicrometer MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that the intrinsic Pucel's noise P, R, and C parameters are not strongly modified by the device scaling. The limitation of the noise performance versus the downscaling process is mainly related to the frequency performance (f/sub max/) of the device. It is demonstrated that for MOSFETs with optimized source, drain, and gate accesses, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high-frequency noise performance of ultra deep-submicrometer MOSFETs.     

Comparison of noise parameters of diffused and ion-implanted microwave transistors

Two types of implanted microwave transistor structures are outlined, and their behaviour is compared with a totally diffused device. Minimum noise figures for the implanted transistors have been obtained in the range 3.6?4.5 dB at a frequency of 4 GHz.     

A unified approach to RF and microwave noise parameter modeling inbipolar transistors

A unified approach to RF and microwave noise parameter modeling in bipolar transistors is presented. Circuit level noise parameters including the minimum noise figure, the optimum generator admittance, and the noise resistance are analytically linked to the fundamental noise sources and the y-parameters of the transistor through circuit analysis of the chain noisy two-port representation. Comparisons of circuit level noise parameters from different physical models of noise sources in the transistor were made against measurements in UHV/CVD SiGe HBTs. A new model for the collector shot noise is then proposed which produces better noise parameter agreement with measured data than the SPICE noise model and the thermodynamic noise model, the two most recent Y-parameter based noise models     

Turn-on speed of grounded gate nMOS ESD protection transistors

The turn-on speed of nMOS transistors (nMOST) is of paramount importance for robust Charged Device Model (CDM) protection circuitry. In this paper the nMOST turn-on time has been measured for the first time in the sub-halve nanosecond range with a commercial e-beam tester. The method may be used to improve CDM-ESD hardness by investigating the CDM pulse responses within circuit. Furthermore it is shown that the CDM results of various protection layouts can be simulated with a SPICE model.     

Boron pocket and channel deactivation in nMOS transistors with SPER junctions

In this paper, we demonstrate the consequences of extension junction formation by low-temperature solid-phase-epitaxial-regrowth in nMOS transistors. Atomistic simulations, experimental device results, sheet resistance, and scanning spreading resistance microscopy data indicate that the high concentration of silicon interstitials associated with the end-of-range defect band promote the local formation of boron-interstitial clusters, and thus deactivate boron in the pocket and channel. These inactive clusters will dissolve after the high concentration silicon interstitial region of the end-of-range defect band has been annihilated. This nMOS requirement is in direct opposition to the pMOS case where avoidance of defect band dissolution is desired, to prevent deactivation of the high concentration boron extension profile.     

DC, RF, and noise characteristics of carbon-doped base InP/InGaAsheterojunction bipolar transistors

The first successful demonstration of high-performance InP/InGaAs heterojunction bipolar transistors utilizing a highly carbon-doped base is reported. The detailed device characteristics including dc, RF, and noise performance have been investigated. For the first time base layers free of hydrogen passivation have been obtained using chemical beam epitaxy. The HBT's showed almost ideal dc characteristics; a gain independent of collector current, a near unity ideality factor, a very small offset-voltage, and a high breakdown voltage. Devices having two 1.5 μm×15 μm emitter fingers exhibited a maximum f_T of 115 GHz and f_max of 52 GHz. The device also exhibited a minimum noise figure of 3.6 dB and associated gain of 13.2 dB at a collector current level of 2 mA where a f_T of 29 GHz and f_max of 23 GHz were measured. The nearly ideal dc characteristics, excellent speed performance, and RF noise performance demonstrate the great potential of the carbon-doped base InP/InGaAs HBT's     

Impact of gate placement on RF power degradation in GaN high electron mobility transistors

We have investigated the RF power degradation of GaN high electron mobility transistors (HEMTs) with different gate placement in the source–drain gap. We found that devices with a centered gate show different degradation behavior from those with the gate placed closer to the source. In particular, centered gate devices degraded through a mechanism that has a similar signature as that responsible for high-voltage DC degradation in the OFF state and is likely driven by electric field. In contrast, offset gate devices under RF power stress showed a large increase in source resistance, which is not regularly observed in DC stress experiments. High-power pulsed stress tests suggest that the combination of high voltage and high current stress maybe the cause of RF power degradation in these offset-gate devices.     

Parasitic modeling and noise mitigation in advanced RF/mixed-signal silicon germanium processes

The potential for highly integrated radio frequency (RF) and mixed-signal (AMS) designs is today very real with the availability cost-effective scaled silicon-germanium (SiGe) process technologies. However, the lack of effective parasitic modeling and noise mitigation significantly restrict opportunities for integration, due to a lack of computer-aided design solutions and practical guidance for designers. This tutorial paper provides a broad in-depth coverage of the key technical areas that designers need to understand in estimating and mitigating IC parasitic effects. A detailed analysis of the parasitic effects in passive devices, the interconnect (including transmission line modeling) and substrate impedance, and isolation estimation is presented-referencing a large number of key publications in these areas.     

High-frequency four noise parameters of silicon-on-insulator-basedtechnology MOSFET for the design of low-noise RF integratedcircuits

An exhaustive experimental study of the high-frequency noise properties of MOSFET in silicon-on-insulator (SOI) technology is presented. Various gate geometries are fabricated to study the influence of effective channel length, gate finger width, and gate sheet resistivity on the four noise parameters. The high level of MOSFET sensitivity to the minimum noise matching condition is demonstrated. From experimental results, optimal ways to realize ultra low noise amplifiers are discussed. The capability of the fully depleted standard SOI CMOS process for realizing low-noise amplifiers for multigigahertz portable communication systems is shown     

双极晶体管关键参数的研究

本文基于双极晶体管的工艺,就如何对电流增益和特征频率两个参数进行优化研究.首先对其进行了器件工艺模拟分析优化,得到模拟特征频率在10 GHz,电流增益为160,而后进行了流片,通过测试得到特征频率为9.5 GHz,电流增益在160以上,最后进行了测试结果和模拟结果的比较分析.     

Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack

A comparison between pMOS and nMOS short channel transistors with high-k dielectric subjected to channel hot-carrier (CHC) stress is presented. Smaller CHC degradation is observed in pMOS devices. At high temperature, the CHC degradation increases for pMOS and nMOS. The temperature dependence of the CHC degradation has been explained, for both transistor types, by considering a larger influence of a bias temperature instability (BTI)-related component of the total CHC induced degradation.     

Impact of advanced processing modules on the low-frequency noise performance of deep-submicron CMOS technologies

Fundamental studies related to the low-frequency (LF) noise performance in semiconductors started more than 40 years ago. In 1957, McWhorter published the first model for the 1/f noise in semiconductors, which is still in use. Whereas for many decades LF noise studies were mainly of fundamental and theoretical interests, in recent years, LF noise characterisation has become a very valuable diagnostic technique for the development of semiconductor materials and devices. Especially, the use of noise characterisation as a tool for reliability predictions has triggered the semiconductor engineering society. Not only the silicon starting material, but also many of the used process modules have a strong impact on the noise performance. This trend is becoming even more pronounced for the advanced deep-submicron technologies. For analog applications of scaled technologies, LF noise may even act as a showstopper. This review, therefore, focuses on the impact of advanced processing on the low-frequency noise behaviour. Both front- and back-end process modules are discussed.     

Advanced CAD tool for noise modeling of RF/microwave field effect transistors with large gate widths

In the millimeter-wave frequency range, electromagnetic (EM) effects can significantly influence a device behavior. As the core of modern communication systems, active devices such as field effect transistors (FETs) require up-to-date models to accurately integrate such effects, especially in terms of noise performance since most of communication systems operate in noisy environments. Furthermore, to keep low-noise amplification over a wide frequency band, the transistor noise resistance R_n must be substantially reduced to make the system insensitive to impedance matching. Since this can be realized through large gate-width devices, a novel large gate-width FET noise model is proposed which efficiently integrates EM wave propagation effects, one of the most important EM effects in mm-wave frequencies.     

White noise in MOS transistors and resistors

The theoretical and experimental results for white noise in the low-power subthreshold region of operation of an MOS transistor are discussed. It is shown that the measurements are consistent with the theoretical predictions. Measurements of noise in photoreceptors-circuits containing a photodiode and an MOS transistor-that are consistent with theory are reported. The photoreceptor noise measurements illustrate the intimate connection of the equipartition theorem of statistical mechanics with noise calculations     

Comments on hot carrier noise in field-effect transistors

Taking into account more rigorously such high field effects as velocity saturation and an increasing free carrier temperature, a new derivation is presented for the output noise of the field-effect transistor. It is shown that for devices with a short channel and a high saturation voltage the equivalent noise resistance can increase considerably above the low field value.     

Performance improvement of self-aligned HfO2/TaN and SiON/TaN nMOS transistors

Direct-etched HfO₂/TaN nMOS transistors were fabricated. The performance of the transistors with aggressively scaled EOT is comparable or better than that of SiO₂/poly transistors. The performance enhancement requires a combination of EOT scaling and an appropriate interface layer control. The performance of the direct-etched TaN gated HfO₂ based transistors is also compared to the performance of similar TaN gated SiON based transistors. It is observed that for equal g_m the leakage is lower for HfO₂ based transistors, despite the lower EOT for the HfO₂ based devices.     

Lateral high-speed bipolar transistors on SOI for RF SoC applications

This paper introduces a novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base. The self-aligned base and emitter regions greatly reduce the parasitic components. In this unique design, the critical dimensions are not limited by lithography resolution. With the control of the SOI film thickness or SWS width, the device can be optimized for higher speed, gain, breakdown, or current drive capability. Furthermore, with no additional mask, both common-emitter and common-collector layout configurations can be realized, providing more flexibility to the circuit design and more compact layout. The experimental f/sub T//f/sub max/ of the high-speed device are 17/28 GHz, the second fastest reported f/sub T/ for lateral bipolar junction transistors (LBJT) so far. As for the high-voltage device, the measured f/sub T//f/sub max/ of 12/30 GHz and BV/sub CEO/ of over 25 V produces a Johnsons product well above 300 GHz /spl middot/V. This figure is currently the closest reported data to the Johnsons limit for lateral BJTs. This technology can easily be integrated with CMOS on SOI. Therefore, it is feasible to build fully complimentary bipolar and MOS transistors on a single SOI substrate to form a true complementary-BiCMOS process. This silicon-based lateral SOI-BJT technology is a promising candidate for realizing future RF SoC applications.