栅极导电层Au迁移导致放大器失效原因分析

针对限幅低噪声放大器使用过程中出现输出不稳定现象,利用扫描电镜和能谱仪对场效应管栅极表面的金属缺失层和栅源之间的金属堆积物进行微观分析,寻找放大器工作不正常的原因。结果表明:场效应管栅极Au层的电迁移,使导线局部电阻增大,温度升高,导致Au的热迁移加重,引起导线出现孔洞和栅源中间堆积金属颗粒,使栅极导线出现开路和栅源极间产生不稳定接触,最终导致场效应管的工作参数漂移和放大器工作不正常。     

VLSI多层互连可靠性第一部分：电迁移失效（一）

一、引言电迁移是指导电材料在电流的作用下产生的物质输运现象，它是引起集成电路失效的一种重要机制。在大电流密度下，由于电迁移作用，可能出现下列导致电路失效的现象：1互连导线中形成空洞，使电阻增加。2空洞贯穿导线的横截面，使电路开路。3形成晶须造成线间或层间短路。4晶须穿破钝化层，形成腐蚀隐患。在电迁移研究中面临着许多难题，影响电迁移的因素十分复杂，其中包括金属的种类、金属股形成条件和结晶结构；金属层间介质和钝化层的种类及淀积条件；电路工作时的电流密度和环境温度；衬底表面形貌；合金效应和尺寸效应等。其次…     

两种高逸出功复合膜材料的AES研究

一、引言:现代大功率微波管已普遍采用无截获栅控电子枪。由于阴影栅一般采取紧贴阴极面的结构,而控制栅与阴极的距离又很近,阴极工作时活性物质极易蒸发和迁移到栅极表面使栅发射,栅截获大量增加,严重影响管子的正常工作。为了解决这一问题,我们利用磁控溅射技术,在栅极上溅射上一层或多层高逸出功材料,用以抑制栅发射。本文介绍了在 Mo 栅极上涂敷 Ta—zr、Fe—Zr 两种     

氧化－削尖自对准多层金属栅的工艺研究

真空平板显示器的底板主要由场发射阴极和金月栅极构成。本文报告了ＴＩ－Ｗ－Ａｕ三层金属栅极代替过去的铝栅，解决了栅与绝绝层ＳｉＯ＿２的附着问题和金属离子迁移问题而又便于压焊引线，本文报告了氧化削尖对准工艺解决了栅阴套准的问题。     

IMEC宣布在栅堆叠和多栅极场效应管器件方面的技术突破

在今年的日本京都2005年6月14日VLSI技术研讨会上，IMEC与其在CMOS工艺上的主要合作伙伴们一起宣布几项在栅堆叠（Gate-stack）和多栅极场效应管（MuGFETs）器件方面的技术突破。多栅极场效应管和栅堆叠技术的结合连同在掩膜版光刻技术的进步也创造了一个新纪录，使一个包含六个完全可工作的晶体管的SRAM单元的面积仅有0．247平方微米。     

无铅焊料的电迁移效应

电迁移是金属原子沿着电流方向的移动。本文阐述了无铅焊料中电迁移的物理特性,由于焊点的特殊几何形状,电流拥挤效应将发生在焊点与导线的接点处;电迁移效应导致无铅焊料中金属间化合物（IMC）的生成与溶解,以及焊点下的金属化层（UBM）的溶解和消耗,使原子发生迁移并会产生孔洞,造成焊点破坏,缩短了焊点平均失效时间（MTTF）,从而带来可靠性问题。     

无铅焊料的研究（4）——电迁移效应

电迁移是金属原子沿着电流方向的移动。阐述了无铅焊料中电迁移的物理特性,由于焊点的特殊几何形状,电流拥挤效应将发生在焊点与导线的接点处;电迁移效应导致无铅焊料中金属间化合物(IMC)的生成与溶解,以及焊点下的金属化层(UBM)的溶解和消耗,使原子发生迁移并会产生孔洞,造成焊点破坏,缩短了焊点平均失效时间(MTTF),从而带来可靠性问题。     

集成SiON栅介质在半导体中的应用与展望

集成电路的快速发展得益于其电路基本单元——场效应管MOSFET电学性能的不断提升。MOSFET器件的关键性能指标是驱动电流Id,驱动电流的大小取决于栅极电容。栅极电容与栅极表面积成正比,与栅介质厚度成反比。因此,通过增加栅极表面积和降低栅介质厚度均可提高栅极电容。随着半导体技术的不断发展,集成电路的集成度也不断提高。     

毫米波工作频率的GaAs FET

据日本《电子技术》1998年第3期报道，日本村田制作所采用GaAs半导体衬底，制作了毫米波工作频率的场效应管。器件采用了该公司独特的GaAs基绝缘栅掺杂沟道异质结构（如图）。其半导体叠层组成为Si掺杂CaAs层（源、漏极下），无掺杂GaAs层（栅极下的绝缘层），Si掺杂InGaAs层（沟道层）。在高频工作下可降低寄生电容和寄生电阻。采用光学曝光的0．2μmT型栅，获得110GHz的特征频率和200GHz以上的最大振荡频率。毫米波工作频率的GaAs FET@孙再吉     

高输出GaAs MESFET

日本NEC公司采用新的结构研制出的GaAs金属半导体场效应管(MESFET)在12GHz频段,微波输出功率达 9W,是同类产品的一倍。新器件采用的新结构为,在半导体电子迁移层和表面保护膜之间形成无杂质的半导体层,此器件在电子层和保护膜之间捕捉电子时不受电流的限制。控制电流的栅极嵌入在无杂质的半导体层内,这样可减     

The Intrinsic Noise Figure of the MESFET Distributed Amplifier

This paper calculates the intrinsic noise figure of the MESFET distributed amplifier assuming, for simplicity, only the Van der Ziel gate and drain noise sources, and produces an expression for the noise figure of a distributed amplifier containing n identical devices. For large gain and Iarge n, a simple expression exists for the product nZ/sub pi g/, where Z/sub pi g/ is the pi-characteristic impedance of the gate line, which minimizes the overall noise figure of the amplifier. This approximate expression is compared with the corresponding expression for a resonant ampfifier using the same MESFET with the same noise sources and with the optimum source impedance for minimum noise figure. Although the resonant amplifier has a slightly lower noise figure, the need to use a circulator to remove the mismatch associated with the optimum source impedance removes this slight advantage.     

Distribution of 1/ƒ noise in an epitaxial GaAs MESFET

A method was devised to determine the distribution of 1/ƒ noise generation in the conducting channel of a field-effect transistor. This newly devised method was applied to an epitaxial GaAs MESFET and the vertical distribution of 1/ƒ noise generation was determined. A noise current source, which represents noise generated in the conducting channel, was assigned to the conventional e_n-i_n representation, in which all the noises are represented by the equivalent noise voltage and current sources at the gate. The magnitude of each noise source was separately determined by measuring the dependence of noise output on the resistance in the gate circuit of the common source amplifier including the FET to be measured. Measurements were performed on a dual gate FET in the frequency range from 0.01 Hz to 25 kHz. It was shown that the more noise is generated in the portion next to the substrate than in the portion at the middle of the active layer.     

A novel GaAs power MESFET with low distortion characteristicsemploying semi-insulating setback layer under the gate

A low distortion GaAs power MESFET has been developed by employing a semi-insulating setback layer under the gate. The setback region was obtained by diffusing chromium from the Cr/Pt/Au gate metal in self-aligned manner. The novel power FET with the setback layer was found to be insensitive to surface trapping effects. They showed only 5-6 percent frequency dispersion of drain current at 1 MHz compared to DC condition. Because of this small frequency dispersion, the typical measurement FET, which has a surface setback layer, with a gate width of 36 mm exhibited 1.5 dB larger output power at 1 dB gain compression point than that of the FET without the setback layer. Moreover, in the π/4 shift-QPSK modulation that has been most popular in digital mobile communication system, the FET exhibited 11 dB smaller adjacent channel leakage power than the conventional one at the output power of 31.5 dBm     

Optimum design of a 4-Gbit/s GaAs MESFET optical preamplifier

An analysis for determining the optimum MESFET gate width to optimize the sensitivity of a high-speed optical preamplifier is presented. A full MESFET model is employed including correlated gate and drain noise sources. The design of an optimum sensitivity monolithic shunt feedback amplifier, including stability requirements, is investigated. The results show that the optimum gate width for minimizing input equivalent noise is significantly larger than earlier simplfied predictions. A sensitivity improvement of 1.2 dB is demonstrated for a 4-Gbit/s MESFET optical amplifier, and results showing the dependence of optimum FET width on photodetector capacitance are described.     

A silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide for high output-power density

We describe a novel silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide (LB-SOI MESFET) and its maximum output power density (P_max). To optimize the surface electric field and improve the breakdown voltage, we eliminated part of the oxide and replaced it with n-type silicon. By creating an n⁺–n region on the source side and modifying the electric field distribution, the breakdown voltage improved by 42% compared to a conventional device. Channel control is realized by varying the depletion layer width underneath the metal gate contact. This modulates the thickness of the conducting channel and thus controls the current between the source and the drain. Continuation of the n-type silicon on top of the buried oxide after the gate metal changes the depletion layer and increases the total channel charge for conduction, so the drain current increases by a factor of five compared to a conventional SOI MESFET. In addition, P_max is increased by a factor of 17.7 with respect to a conventional structure, which is important for large-signal analog applications. Consequently, our novel LB-SOI MESFET has superior electrical characteristics.     

Calculation of microwave performance of buffer layer gate GaAs MESFET's

The microwave performance of a GaAs MESFET, where a buffer layer of a low carrier concentration is inserted between the gate metal and the channel layer, is calculated and compared with that of a conventional MESFET. It is found that the use of such a high-resistivity buffer layer contributes to a great improvement of the microwave performance of the GaAs MESFET, especially in fTandf_{max}.     

InP MESFET with In0.53Ga0.47As/InP heterostructure contacts

Source and drain contacts for an InP MESFET were prepared by an Au/Ni/In0.53Ga0.47As/InP layered structure, without a metal alloying process. A highly conductive In0.53Ga0.47As layer grown on an InP active layer reduced the gate-source resistance. A maximum DC transconductance of 16 mS has been obtained for an InP MESFET with 1.2×190 ?m gate dimensions and a pinch-off voltage of ?0.7 V.     

A self-aligned gate GaAs MESFET with p-pocket layers forhigh-efficiency linear power amplifiers

This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFET's, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz π/4-shift QPSK modulated input     

The Matched Feedback Amplifier: Ultrawide-Band Microwave Amplification with GaAs MESFET's

An ultrawide-band amplifier module has been developed that covers the frequency range from 350 MHz to 14 GHz. A minimum gain of 4 dB was obtained across this 40:1 bandwidth at an output power of 13 dBm. The amplifier makes use of negative and positive feedback and incorporates a GaAs MESFET that was developed with special emphasis on low parasitics. The transistor has the gate dimensions 800 by 1 mu m. The technology and RF performance of the GaAs MESFET are discussed, as are the design considerations and performance of the single-ended feed-back amplifier module.     

A Low Distortion and Low Dissipation Power Amplifier with Gate Bias Control Circuit for Digital/Analog Dual-Mode Cellular Phones

A power amplifier operating at 3.3 V. has been developed for CDMA/AMPS dual-mode cellular phones. It consists of linear GaAs power MESFET's, a new gate bias control circuit, and an output matching circuit which prevents the drain terminal of the second MESFET from generating the harmonics. The relationship between the intermodulation distortion and the spectral regrowth of the power amplifier has been investigated with gate bias by using the two-tone test method and the adjacent channel leakage power ratio (ACPR) method of CDMA signals. The dissipation power of the power amplifier with a gate bias control circuit is minimized to below 1000 mW in the range of the low power levels while satisfying the ACPR of less than ?26 dBc for CDMA mode. The ACPR of the power amplifier is measured to be ?33 dBc at a high output power of 26 dBm.