A low-power 200-MHz receiver for wireless hearing aid devices

The design of a low-power receiver for a wireless hearing aid system working in the 174-223-MHz range and its implementation in a 0.8-/spl mu/m BiCMOS technology is shown. The chip comprises a low-noise amplifier, an RF mixer, a variable-gain IF amplifier, and a demodulator. The latter consists of a digital phase shifter and I/Q IF mixers, fifth-order Bessel filters, and dc amplifiers. Measurements demonstrate that merely 667 /spl mu/A is consumed for the reception of an 8-ary phase-shift keying signal with a data rate of 336 kb/s. The receiver works with different modulation formats, including those carrying information in the amplitude.     

A 200-MHz sub-mA RF front end for wireless hearing aid applications

A hearing-aid system with RF connection between both ear-pieces is described and its transceiver is introduced. A suitable 200-MHz RF front end has been implemented in a 0.8-μm BiCMOS technology. Low power consumption and area constraint were key requirements. The chip comprises a low noise amplifier (LNA), a single balanced mixer, a varactor tuned LC local oscillator with buffer and a 16/17 dual-modulus prescaler. The LNA has a measured gain of 17.5 dB at 200 MHz. The conversion g_m of the mixer is 1.88 mS. The overall voltage gain and noise figure are 26 dB and 5.2 dB, respectively. The voltage-controlled oscillator's (VCO's) phase noise is -104.7 dBc/Hz at an offset of 24 kHz     

Logarithmic data converter suitable for hearing aid applications

A novel method for analogue-to-digital conversion with compressive /spl mu/-law transfer characteristic, suitable for hearing aid applications, is presented. The proposed method can be realised as low-power tunable analogue-to-digital converters in both pipeline and algorithmic architectures and is integratable in CMOS technology.     

Wavelet-based nonlinear AGC method for hearing aid loudnesscompensation

Hearing impairment can often be corrected by medical or surgical treatment, provided the loss is not due to cochlear pathology (sensorineural loss). For sensorineural loss, the only corrective action is to wear a hearing aid. Many perceptual differences between normal and sensorineural hearing-impaired listeners are due to differences in the dB levels at which sound is detected by the ear (auditory threshold) and the associated dynamic range over which it is comfortable to listen to (loudness sensation). To adequately compensate for this, the processing of the auditory signal should be nonlinear and time-varying. Two wavelet-based compression algorithms have been developed: automatic gain control (AGC) with linear amplification and nonlinear compression AGC. The nonlinear AGC is a compression algorithm, which models loudness sensation. The wavelet transform separates the input into seven frequency bands corresponding to the critical bands of the human auditory system. For each frequency band, multiplying the wavelet coefficients by the gain can amplify or compress nonlinearly and smoothly, depending on the signal level, time and spectrum. Results suggest that the nonlinear approach, while maintaining the general spectral structure of the signal, is perceptually superior to linear AGC and compensates better for audibility loss     

Ultra-low-power DLMS adaptive filter for hearing aid applications

We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate the system at a lower clock rate and reduced supply voltage while maintaining the same throughput. Pseudo nMOS logic operating in the subthreshold region (subpseudo nMOS) provided better power-delay product than subthreshold CMOS (sub-CMOS) logic. Simulation results show that the DLMS adaptive filter can operate at 22 kHz using a 400-mV supply voltage to achieve 91% improvement in power compared to a nonparallel, CMOS implementation. To validate the robust operation of subthreshold logics, a 0.35 /spl mu/m, 23.1 kHz, 21.4 nW, 8/spl times/8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating process, supply and temperature variations. The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors.     

Analog circuits for a single-chip infrared controlled hearing aid

All analog circuits for a remotely controllable subminiature hearing aid are presented. It is feasible to integrate all circuits together with an I²L decoder on a single bipolar chip. The volume level and the cutoff frequency of a high-pass filter can be controlled. Besides, the device can be remotely switched at microphone and telephone coil, and switched into a standby mode. All circuits presented have been tested with a semicustom realization.     

Acoustic readout circuit system without highpass filter for hearing aid

A readout circuit system is designed for a hearing aid without a highpass filter. The system achieved an SNR of 42.3 dB and a third-order harmonic distortion ratio of 58 dB when the input voltage was 60 muV to attain output of 0.48 V. For 57.9 and 74.8 dB gains, the bandwidths were 60 Hz-106 kHz and 100 Hz-20 kHz, respectively. The 1.65 mm² system chip consumes 222 muW in 0.35 mum CMOS process     

Design of high-performance digital hearing aid processor

A digital hearing aid processor (DHAP) chip built around a general-purpose 16 bit DSP core is presented. The designed DHAP performs a nonlinear loudness correction of eight frequency bands based on acoustic measurements. The DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the chip has a low power feature and 5,500×5,000 μm² dimensions that make it suitable for wearable hearing aids     

Constructing a videophone for the hearing impaired using MPEG-4tools

The Lip Telephone is a special videoconferencing system built by the authors with tools provided by the MPEG-4 audio-visual standard. The videophone achieves high-fidelity representation in the area of the speaker's mouth, letting lip readers communicate over a standard telephone connection or the Internet     

Audiogram matching in hearing aid using approximate arithmetic

Multidimensional Systems and Signal Processing - Filter banks are the major signal processing blocks that dissipate large amount of power in a portable digital hearing aid device. The power...     

3-D shape modeling for hearing aid design [Applications Corner]

Advances in 3-D scanning and fabrication hardware as well as 3-D geometric design software have transformed a once laborintensive manual manufacturing into an efficient digital process for hearing aid design, resulting in higher quality, reduced cost, and better fitting devices. Future work in this field will continue to focus on increasing automation until the process is fully automatic.     

High performance continuous variable bandwidth digital filter design for hearing aid application

A low complexity, low delay reconfigurable digital filter structure for hearing aids is proposed in this paper. The main objective is to match a given human audiogram, with minimum error. The high computational complexity in the conventional uniform and non-uniform filter bank techniques, probes to shift the design paradigm towards variable filter structure. In this paper, Farrow structure based design is used to realize an arbitrary sample rate converter, making use of a differentiator based model, by which the bandwidth can be continuously varied. The proposed design also considers the importance of the power, area, and” delay in such a critical scenario. Exhaustive comparisons are performed with the existing literature on audiogram matching, and our design is very competitive when compared to the designs in the literature, not only with respect to the matching error but also with respect to area, power dissipation, and hardware complexity.     

Integrated frequency-domain digital hearing aid with the lapped transform

This paper presents a frequency domain digital hearing aid based upon the new lapped transform, which has the ability to eliminate the blocking effects inherent in traditional frequency domain filtering. Incorporated into the new digital hearing aid are the functions of frequency shaping, acoustic feedback cancellation and periodic noise reduction.<>     

A programmable analog hearing aid system-on-chip with frequency compensation

An analog hearing aid with the function of frequency compensation is proposed and implemented considering the human factors. Introducing the current-mode technique, a filter designed by the state space methodology is integrated in the hearing aid to offer the function which only appears in the DSP unit of digital hearing aid. Combined with the filter embedded in the driver circuit adopting the minimum current selecting technique, the enhance frequency compensation can well match to the common low-frequency hearing loss with a stopband attenuation of 80 dB/dec. Moreover, a low-noise automatic gain control (AGC) is presented to improve the programmability with discreet gains, knee points and compression ratios. To enhance the comfortable level, the attack time and release time is set 20 and 100 ms with a peak detector. The input-referred noise is below 5 μVrms. The hearing aid can drive a 16 Ω receiver at the supply voltage of 1 V. The die area is 2.3 × 1.5 mm² (AGC) and 0.93 × 0.86 mm² (driver) in a 0.13 μm standard CMOS process and 1 × 1 mm² (filter) in a 0.35 μm standard CMOS process.     

A set of four ICs in CMOS technology for a programmable hearing aid

A four-chip system developed for a programmable hearing aid is presented. It combines E²PROM (electrically erasable programmable read-only memory) memories with a control logic, low-noise preamplifiers, AGC (automatic gain control) amplifiers, SC (switched-capacitor) filters, voltage multipliers, and an output amplifier of the pulse-width type. The implementation of the critical parts is explained. The 3-μm self-aligned-contacts MOS technology of the Faselec company is used. The system is supplied by a single 1.3-V battery and its typical current consumption is 1.5 mA. The whole system can be connected to a computer     

一种用于数字助听器SoC的高性能低功耗、可配置自动增益控制环路

A low-power,configurable auto-gain control loop for a digital hearing aid system on a chip(SoC) is presented.By adopting a mixed-signal feedback control structure and peak detection and judgment,it can work in automatic gain or variable gain control modes through a digital signal processing unit.A noise-reduction and dynamic range(DR) improvement technique is also used to ensure the DR of the circuit in a low-voltage supply.The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process.The measurement results show that in a 1 V power supply,1.6 kHz input frequency and 200 mVp-p,the SFDR is 74.3 dB,the THD is 66.1 dB,and the total power is 89 μW,meeting the application requirements of hearing aid SoCs.     

Microvibration transducer using silicon elastic body for an implantable middle ear hearing aid

In this paper, the microelectromagnetic vibration transducer is presented for the use of an implantable middle ear hearing aid, characterized by its small size, high efficiency and selective frequency bandwidth. In order to construct this, a new type of electromagnetic vibration transducer, composed of wound coil, a permanent magnet and a four-beam cross type silicon elastic body, is required. The fabricated transducer is useful for the application of 1–5 mA of a current source, 0.5–55 dyn of a vibration peak force and at a frequency range of a 100–7000 Hz.     

Capacity and lattice strategies for canceling known interference

We consider the generalized dirty-paper channel Y=X+S+N,E{X/sup 2/}/spl les/P/sub X/, where N is not necessarily Gaussian, and the interference S is known causally or noncausally to the transmitter. We derive worst case capacity formulas and strategies for "strong" or arbitrarily varying interference. In the causal side information (SI) case, we develop a capacity formula based on minimum noise entropy strategies. We then show that strategies associated with entropy-constrained quantizers provide lower and upper bounds on the capacity. At high signal-to-noise ratio (SNR) conditions, i.e., if N is weak relative to the power constraint P/sub X/, these bounds coincide, the optimum strategies take the form of scalar lattice quantizers, and the capacity loss due to not having S at the receiver is shown to be exactly the "shaping gain" 1/2log(2/spl pi/e/12)/spl ap/ 0.254 bit. We extend the schemes to obtain achievable rates at any SNR and to noncausal SI, by incorporating minimum mean-squared error (MMSE) scaling, and by using k-dimensional lattices. For Gaussian N, the capacity loss of this scheme is upper-bounded by 1/2log2/spl pi/eG(/spl Lambda/), where G(/spl Lambda/) is the normalized second moment of the lattice. With a proper choice of lattice, the loss goes to zero as the dimension k goes to infinity, in agreement with the results of Costa. These results provide an information-theoretic framework for the study of common communication problems such as precoding for intersymbol interference (ISI) channels and broadcast channels.     

Direct interference canceling for two-electrode biopotential amplifier

A two-electrode biopotential amplifier, though simpler than a three-electrode amplifier, has problems rejecting 60 Hz power-line interference due to the imbalance of electrode–skin impedance. A direct interference canceling (DIC) scheme to reject 60 Hz interference for a two-electrode biopotential amplifier is proposed. The DIC scheme cancels differential-mode interference directly by adding to the interference to be canceled a feedback signal that has the same magnitude and frequency as the interference, but that has phase shifted 180°. When the DIC is started by closing a switch, transient interference appears, which decreases within several seconds. In steady state, the DIC amplifier rejects a very narrow bandwidth (BW) centered at the interference frequency. The proposed circuit was implemented and the DIC operation yielded 54 dB interference canceling with 0.6 Hz rejection BW.