A 200-MHz seventh-order equiripple continuous-time filter by designof nonlinearity suppression in 0.25-μm CMOS process

Seventh-order equiripple filter with cutoff frequency of 200 MHz is developed in CMOS 0.25-μm process. A new design method has been adopted to obtain enough accuracy and linearity in high-frequency operation. Optimal device sizes are determined, which maximize the accuracy. The most suitable filter configuration is determined, which suppresses the influence of the nonlinearity of the transconductors over the linearity of the filter. Experimental results satisfied group delay variation of ±5% and achieved total harmonic distortion of less than 1% for 800 mV_ppd differential input     

70-MHz 2-μm CMOS bit-level systolic array median filter

An algorithm for VLSI median filtering of one-dimensional signals of complexity linearly dependent on the filter window length is described. The algorithm is implemented as a bit-level systolic array (BLSA), in order to achieve high performance. A single-chip median filter characterized by a window length of 25 8-b samples, and by operation on three interleaved independent sequences for a total of 75 samples, is presented as a demonstration of the concept. The throughput relevant to one sequence is 1/3 for this chip, whereas the theoretical maximum allowed by the algorithm is 1/2. Prototypes designed with a 2-μm CMOS technology have been successfully tested at a clock frequency over 70 MHz     

A monolithic analog video comb filter in 1.2-μm CMOS

A fully integrated comb filter for luminance/chrominance (Y/C) separation of NTSC video signals is fabricated using a standard 1.2-μm double-poly CMOS technology. This paper demonstrates its use of analog RAM structures in the realization of video line delays. Information is stored and retrieved using switched-capacitor techniques optimized for operation in a parasitic dominated environment. Fixed pattern noise is avoided through the use of serial data paths whenever possible, necessitating the use of a G_m-enhanced amplifier and techniques to improve the feedback factor. The 11.7 mm² adjustment-free circuit, which requires a single clock and reference current, dissipates 170 mW at 5 V and yields an SNR of 51 dB and frequency response flat within 1.1 dB to 4.2 MHz     

A 250-MHz wave pipelined adder in 2-μm CMOS

Wave pipelining (also known as maximal rate pipelining) is a timing methodology used in digital systems to increase the number of effective pipelined stages without increasing the number of physical registers in the system. Using this technique, new data are applied to the inputs of a combinational block before the previous outputs are available, thus effectively pipelining the combinational logic. Achieving a high degree of wave pipelining in CMOS technology requires careful study of delay balancing technique involving circuit design, layout method, and testing structure. A 16-b parallel adder, utilizing wave pipelining is implemented with MOSIS 2-μm technology and test results of fabricated devices show more than nine times speedup over nonpipelined operation     

Quaternary logic circuits in 2-μm CMOS technology

Novel quaternary logic circuits, designed in 2-μm CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra has been designed and fabricated. The prototype chip occupies an area of 4.84 mm², is timed with a 2.2-MHz clock, and consumes 93 mW of power     

A 0.5-μm CMOS T/R switch for 900-MHz wireless applications

A single-pole double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-μm CMOS process. An analysis shows that substrate resistances and source/drain-to-body capacitances must be lowered to decrease insertion loss. The switch exhibits a 0.7-dB insertion loss, a 17-dBm power 1-dB compression point (P_{1 dB}), and a 42-dB isolation at 928 MHz. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by dc biasing the transmit and receive nodes, which decreases the capacitances while increasing the power 1-dB compression point. The switch has adequate insertion loss, isolation, P_{1 dB}, and IP₃ for a number of 900-MHz ISM band applications requiring a moderate peak transmitter power level (~15 dBm)     

A 2-ns detecting time, 2-μm CMOS built-in current sensingcircuit

Built-in current testing is known to enhance the defect coverage in CMOS VLSI. An experimental CMOS chip containing a high-speed built-in current sensing (BICS) circuit design is described. This chip has been fabricated through MOSIS 2-μm p-well CMOS technology. The power bus current of an 8×8 parallel multiplier is monitored. This BICS detects all implanted short-circuit defects and some implanted open-circuit defects at a clock speed of 30 MHz (limited by the test setup). SPICE3 simulations indicate a defect detection time of about 2 ns     

A concurrent error detection IC in 2-μm static CMOS logic

When a comprehensive fault model is considered, static CMOS VLSI has long been prohibited from realizing concurrent error detecting (CED) circuits due to the unique analog faults (bridging and stuck-on faults). In this paper, we present the design, fabrication and testing of an experimental chip containing the integration of a totally self-checking (TSC) Berger code checker and a strongly code disjoint (SCD) built-in current sensor (BICS). This chip was fabricated by MOSIS using 2 μm p-well CMOS technology. In chip tests, all implanted faults, including analog faults, were detected as expected. We also show that the self-exercising mechanism of the SCD BICS is indeed functioning properly. This is the first demonstration of a working static CMOS CED chip     

一种适用于生物电信号处理的全集成五阶Gm-C低通滤波器

传统的Gm-C滤波器OTA输入晶体管大多工作在饱和区,存在输入动态范围较小和跨导值较大等不足,难以满足生物医学电信号处理滤波器所要求的超低截止频率、低功耗与大输入动态范围等要求,采用将输入晶体管钳位到线性工作区的方法,设计了跨导线性可调的OTA以提高滤波器能够处理的信号幅度。并应用该OTA综合了一种五阶Gm-C超低频低通滤波器。仿真结果表明,该滤波器在1.8 V电源,800 m Vpp输入条件下实现了283 Hz的超低低通角频率,-6.4 d B的带内增益,51 d B的三次谐波失真,功耗仅为22μW,适用于可穿戴式生物医学电信号读取电路。     

A CMOS mainframe processor with 0.5-μm channel length

A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 μm. The chip set consists of the instruction and the fixed-point processor, two cache chips with 16 KB of data and instructions, and the floating-point processor. The chips are implemented in a 1.0-μm technology with three layers of metal. An automatic design system based on the sea-of-gates technique and the standard cell approach was used. The worst-case operating frequency of the chip set is 35 MHz (typically 50 MHz). Four chips of the processor are packaged on a ceramic multichip module. Level-sensitive scan design, built-in self-test, and parity check guarantee high test coverage and reliability     

A CMOS 140-mW fourth-order continuous-time low-pass filter stabilized with a class AB common-mode feedback operating at 550 MHz

A 550-MHz linear-phase low-pass continuous-time filter is described. The operational transconductance amplifier (OTA) is based on complementary differential pairs in order to achieve high-frequency operation. A common-mode feedback (CMFB) based on a Class AB amplifier with improved stability at high frequencies is introduced. Results for the stand alone OTA show a unity gain frequency of 1 GHz while the excess phase is less than 5/spl deg/. The filter is based on G/sub m/-C biquads and achieves IM3 <-40 dB for a two-tone input signal of -10 dBm each. The power consumption of the fourth-order filter is 140 mW from supply voltages of /spl plusmn/1.65 V. The chip was fabricated in a standard 0.35-/spl mu/m CMOS technology.     

A 0.25-μm CMOS 0.9-V 100-MHz DSP core

This paper describes a 0.25-μm CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-μm CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs     

A switched-current, switched-capacitor temperature sensor in0.6-μm CMOS

A temperature-to-digital converter is described which uses a sensor based on the principle of accurately scaled currents in the parasitic substrate p-n-p in a standard fine-line CMOS process. The resulting PTAT δV_BE signal is amplified in an auto-zeroed switched-capacitor circuit, sampled, and converted to a digital output by a low-power 10-bit SAR ADC providing a resolution of 0.25° from -55°C to 125°C with an error of less than 1°. A single adjustment of temperature error is provided for wafer probe. No further calibration is required. A switching bandgap reference circuit will also be described which uses similar techniques to generate an accurate low-noise reference voltage for the ADC. The circuits are part of a multichannel data-acquisition system where other input voltages must also be sampled and measured, and so the speed and power of the ADC is not determined by the temperature sensor alone. For continuous operation, the supply current is 1 mA, but a low-power mode is provided where the part is normally in shut down and only powers up when required. In this mode, the average power supply current at 10 conversions/s is 0.3 μA. The supply voltage is 2.7-5.5 V     

A low-noise, 900-MHz VCO in 0.6-μm CMOS

This paper describes a low-noise, 900-MHz, voltage-controlled oscillator (VCO) fabricated in a 0.6-μm CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. The VCO operates at 750 MHz to 1.2 GHz, and the tuning range is as large as 50%. The measured results of the phase noise are -101 dBc/Hz at 100-kHz offset and -117 dBc/Hz at 600-kHz offset from the carrier frequency. This value is comparable to that of LC-based integrated oscillators. The oscillator consumes 10 mA from a 3.0-V power supply. A prototype frequency synthesizer with the VCO is also implemented in the same technology, and the measured phase noise of the synthesizer is -113 dSc/Hz at 100-kHz offset     

A low-resistance self-aligned T-shaped gate for high-performancesub-0.1-μm CMOS

This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1-μm region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 μm to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 μm. Furthermore, we experimentally show that the high circuit speed of a sub-0.1-μm gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability     

A new cobalt salicide technology for 0.15-μm CMOS devices

A new cobalt (Co) salicide technology for sub-quarter micron CMOS transistors has been developed using high-temperature sputtering and in situ vacuum annealing. Sheet resistance of 11 Ω/□ for both gate electrode and diffusion layer was obtained with 5-nm-thick Co film. No line width dependence of sheet resistance was observed down to 0.15-μm-wide gate electrode and 0.33-μm-wide diffusion layer. The high temperature sputtering process led to the growth of epitaxial CoSi ₂ layers with high thermal stability. By using this technology 0.15 μm CMOS devices which have shallow junctions were successfully fabricated     

A 70-MHz 1.2-μm CMOS 16-point DFT processor

A chip architecture designed to compute a 16-point discrete Fourier transform (DFT) using S. Winograd's algorithm (1978) every 457 ns is presented. The 99500-transistor 1.2-μm chip incorporates arithmetic, control, and input/output circuitry with testability and fault detection into a 144-pin package. A throughput of 2.3×10¹² gate-Hz/cm² and 79-million multiplications/s is attained with 70-MHz pipelined bit-serial logic. Combined with similar chips computing 15- and 17-point DFTs, 4080-point DFTs can be computed every 118 μs. Using the 16- and 17-point chips, 272×272-point complex data imagery can be transformed in 4.25 ms. A 24-bit block floating-point data representation combined with an adaptive scaling algorithm delivers a numerical precision of 106 dB (17.6 bits) after computing 4080-point DFTs     

An 0.8-μm CMOS mixed analog-digital integrated audiometricsystem

This paper presents a dual-channel fully integrated audiometric system, which generates the complete set of audio and control signals required for exhaustive audiometric tests. The system includes a novel signal generator, based on the direct digital synthesis technique, which fulfils the requirements of advanced audiometric tests. The proposed system faces two different problems, namely, the generation of a finely tunable pure sinewave and the generation of noise signals with a controlled spectrum. To achieve tuning capabilities down to 1 Hz at 20 kHz and 15 μHz at 100 Hz, a fractional division of a 40-MHz master clock based on noise-shaping techniques is performed. Moreover, for noise generation, a novel circuit based on pseudorandom sequences combined with analog switched-capacitor filters is used. The chip is fabricated in a 0.8 μm CMOS process and occupies a 24.2 mm² silicon area. It consumes 45 mW from a single 5 V power supply and achieves less than -90 dB crosstalk between the channels     

0.15-μm RF CMOS technology compatible with logic CMOS forlow-voltage operation

Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption. In this paper, a 0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation is described. Because the fabrication process is the same as the high-speed logic CMOS, manufacturability of this technology is excellent. Some of the passive elements can be integrated without changing the process and others can be integrated with the addition of a few optional processes. Mixed RF and logic CMOS devices in a one-chip LSI can be realized with relatively low cost. Excellent high-frequency characteristics of small geometry silicon MOSFETs with low-power supply voltage are demonstrated. Cutoff frequency of 42 GHz of n-MOSFETs, which is almost the same level at that of general high-performance silicon bipolar transistors, was obtained. N-MOSFET's maintained enough high cutoff frequency of 32 GHz even at extremely low supply voltage of 0.5 V. Moreover, it was confirmed that degradation of minimum noise figure for deep submicron MOSFETs with 0.5 V operation is sufficiently small compared with 2.0 V operation. These excellent high-frequency characteristics of small geometry silicon MOSFETs under low-voltage operation are suitable for mobile telecommunications applications     

High-voltage devices for 0.5-μm standard CMOS technology

The feasibility of the smart voltage extension (SVX) technique featuring complementary high-voltage devices without any modifications of the process steps of an 0.5-μm standard CMOS technology is discussed here. This letter focuses on the optimization of the breakdown voltage of the HVNMOS as well as the possible implementation of the HVPMOS. Different high-voltage options with increasing process modification steps are discussed as a function of the required high-voltage capabilities