Optimal bus sizing in migration of processor design

The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor to next generation technology. In this paper, timing optimization of signal buses is performed by resizing and spacing individual bus wires, while the area of the whole bus structure is regarded as a fixed constraint. Four different objective functions are defined and their usefulness is discussed in the context of the layout migration process. The paper presents solutions for the respective optimization problems and analyzes their properties. In an optimally-tuned bus layout, after optimizing the most critical signal delay, all signal delays (or slacks) are equal. The optimal solution of the MinMax problem is always bounded by the solution of the corresponding sum-of-delays problem. An iterative algorithm to find the optimally-tuned bus layout is presented. Examples of solutions are shown, and design implications are derived and discussed.     

Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion

Capacitive crosstalk between adjacent signal wires has significant effect on performance and delay uncertainty of point-to-point on-chip buses in deep submicrometer (DSM) VLSI technologies. We propose a hybrid polarity repeater insertion technique that combines inverting and non-inverting repeater insertion to achieve constant average effective coupling capacitance per wire transition for all possible switching patterns. Theoretical analysis shows the superiority of the proposed method in terms of performance and delay uncertainty compared to conventional and staggered repeater insertion methods. Simulations at the 90-nm node on semi-global METAL5 layer show around 25% reduction in worst case delay and around 86% delay uncertainty minimization compared to standard bus with optimal repeater configuration. The reduction in worst case capacitive coupling reduces peak energy which is a critical factor for thermal regulation and packaging. Isodelay comparisons with standard bus show that the proposed technique achieves considerable reduction in total buffers area, which in turn reduces average energy and peak current. Comparisons with staggered repeater which is one of the simplest and most effective crosstalk reduction techniques in the literature show that hybrid polarity repeater offers higher performance, less delay uncertainty, and reduced sensitivity to repeater placement variation.      

Fault model for on-chip communication and joint equalization and special spacing rules for on-chip bus design

Achieving high speed and reliability is a key challenge in on-chip bus design. To address the challenge, in this paper we propose a fault model for on-chip communication and further develop a new joint scheme which integrates an equalization technique and special spacing rules for improving the speed and communication reliability for on-chip buses. The proposed equalizer employs a variable threshold inverter whose switching threshold is adjusted as a function of the past output of the buses to achieve high-speed and high-reliability of the buses. Special spacing rules use the sufficient spacing between the adjacent wires to mitigate the crosstalk effect from the adjacent wires. The joint scheme equalization and special spacing rules exploits their respective advantages to further improve the speed and communication reliability of the buses. The simulation results show that the joint scheme equalization and increasing spacing of the uncoded bus can reduce 50% delay and save 42% power only with 52% area overhead compared with the minimum-spaced uncoded bus. The bit error rate of the bus can be improved from 10^?5 to 10^?24.     

A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation

This paper addresses the critical problem of global wire optimization for nanometer scale very large scale integration technologies, and elucidates the impact of such optimization on power dissipation, bandwidth, and performance. Specifically, this paper introduces a novel methodology for optimizing global interconnect width, which maximizes a novel figure of merit (FOM) that is a user-defined function of bandwidth per unit width of chip edge and latency. This methodology is used to develop analytical expressions for optimum interconnect widths for typical FOMs for two extreme scenarios regarding line spacing: 1) spacing kept constant at its minimum value and 2) spacing kept the same as line width. These expressions have been used to compute the optimal global interconnect width and quantify the effect of increasing the line width on various performance metrics such as delay per unit length, total repeater area and power dissipation, and bandwidth for various International Technology Roadmap for Semiconductors technology nodes.     

Optimal global interconnects for GSI

Performance of a high-speed chip is largely affected by both latency and bandwidth of global interconnects, which connect different macrocells. Therefore, one of the important goals is to design high-bandwidth and fast buses that connect a processor and its on-chip cache memory or link different processors within a multiprocessor chip. In this paper, the width of global interconnects is optimized to achieve a large "data-flux density" and a small latency simultaneously. Data-flux density is the product of interconnect bandwidth and reciprocal wire pitch, which represents the number of bits per second that can be transferred across a unit-length bisectional line. The optimal wire width, which maximizes the product of data-flux density and reciprocal latency, is independent of interconnect length and can be used for all global interconnects. It is rigorously proved that the optimal wire width is the width that results in a delay that is 33% larger than the time-of-flight (ToF). Using the optimal wire width decreases latency, energy dissipation, and repeater area considerably, compared to a sub-optimal wire width (e.g., 42% smaller latency, 30% smaller energy-per-bit, and 84% smaller repeater area compared with the W/sub opt//2 case) at the cost of a small decrease in data-flux density (e.g., 14% smaller compared with W/sub opt//2 case). A super-optimal wire width, however, causes a slight decrease in latency (e.g., 14% for 2W/sub opt/) at the cost of a large decrease in data-flux density (e.g., 35% for 2W/sub opt/).     

Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing

The use of deep-submicrometer (DSM) technology increases the capacitive coupling between adjacent wires leading to severe crosstalk noise, which causes power dissipation and may also lead to malfunction of a chip. In this paper, we present a technique that reduces crosstalk noise on instruction buses. While previous research focuses primarily on address buses, little work can be applied efficiently to instruction buses. This is due to the complex transition behavior of instruction streams. Based on instruction sequence profiling, we exploit an architecture that encodes pairs of bus wires and permute them in order to optimize power and noise. A close to optimal architecture configuration is obtained using a genetic algorithm. Unlike previous bus encoding approaches, crosstalk reduction can be balanced with delay and area overhead. Moreover, if delay (or area) is most critical, our architecture can be tailored to add nearly no overhead to the design. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. The results show that our approach can reduce crosstalk up to 50.79% and power consumption up to 55% on instruction buses.     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays

Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering at interior points in the wire. This paper presents a framework for designing and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance using HSPICE-derived delays. Given a target physical wire length, width, and spacing, the method determines the number, size, and position of buffers required to obtain the fastest signal velocity for programmable interconnect. While traditional hand-calculations used for ideal repeater placement can be used, they are not very accurate and ignore practical constraints such as the overhead effects of front-end multiplexing and driving logic, “finite” wire length, and a discrete number of repeaters. A metric introduced during the design is the “path delay profile”, or the arrival time of a signal at different points of a long wire. This method is used to design buffering strategies for interconnect based on 0.5, 2, and 3 mm wire lengths in 180 nm technology. These interconnect designs are coded into VPR along with an improved timing analyzer which accurately determines the “path delay profile” arrival times. Using VPR, average critical-path delay is reduced by 19% for 0.5 mm wires and by up to 46% for 3mm wires over previous designs.

Global interconnect width and spacing optimization for latency, bandwidth and power dissipation

This paper addresses a novel methodology optimizing global interconnect width and spacing for International Technology Roadmap for Semiconductors technology nodes. Global interconnects with and without buffer insertion are considered. The effects of the width and spacing of global interconnects on performance, such as delay, bandwidth, total repeater area and energy dissipation, are analyzed. The product of delay and bandwidth is used as the figure of merit for simultaneous short latency and large bandwidth and the proposed methodology can optimize global interconnects for the maximal figure of merit. It is demonstrated that buffers should not be inserted in global interconnects if interconnect length is shorter than a critical length, which is a constant for a given technology. For global interconnects with buffer insertion, the optimal width and spacing have analytical expressions and are constants for a given technology. For global interconnects without buffer insertion, the optimal width and spacing are dependent on both the technology parameters and interconnect length and can be computed numerically.     

Electromagnetic response of two crossing, infinitely long, thinwires

The electromagnetic coupling of two crossed thin wires of infinite length is considered. Two coupled integral equations are obtained, given in terms of generalized impedance functions, for the spectral currents flowing in each wire. The wires may be in a homogeneous medium or over a half-space. The numerical implementation focuses, however, only on the former. The numerical solution may be obtained by either applying moment or multiple scattering methods. The solution obtained from the method of moments is applicable for any wire spacing. Obversely, the multiple scattering method leads to a convenient matrix series solution, which shows that the coupling between wires is proportional to 1/d ² (where d is the wire separation) plus higher order scattering terms     

Serial-Link Bus: A Low-Power On-Chip Bus Architecture

As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of bus lines of the conventional parallel-line bus (PLB) architecture by multiplexing each m-bits onto a single line. This bus architecture, the serial-link bus (SLB), transforms an n-bit conventional PLB into an n/m-line (serial link) bus. The advantage of SLBs is that they have fewer lines, and if the bus width is kept the same, SLBs will have a larger line pitch. Increasing the line width has a twofold reduction effect on the line resistance; as the resistivity of sub-100 nm wires drops significantly, the line width increases. Also, increasing the line width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m _opt and an optimum width to pitch ratio eta_opt exist, which minimizes the bus energy dissipation and maximizes the bus throughput per unit area. The optimum degree of multiplexing and optimum width-to-pitch ratio for maximum throughput per unit area and minimum energy dissipation for the 25-130-nm technologies was determined in this paper. Also, an encoding technique was proposed and implemented to reduce the switch activity penalty due to serialization. HSPICE simulations show that for the same throughput per unit area as conventional parallel-line data buses, the SLB architecture reduces the energy dissipation by up to 31% for a 64-bit bus implemented in an intermediate metal layer of a 50-nm technology, and a reduction of 53% is projected for a 25-nm technology.     

Analysis and optimization of shielded RLC global interconnects for gigascale integration

Compact physical models are presented for on-chip double-sided shielded transmission lines, which are mainly used for long global interconnects where inductance effects should not be ignored. The models are then used to optimize the width and spacing of long global interconnects with repeater insertion. The impacts of increasing line width and spacing on various performance parameters such as delay, data-flux density, power dissipation and total repeater area are analysed. The product of data-flux density and reciprocal delay per unit length are defined as a figure of merit (FOM). By maximizing the FOM, the optimal width and spacing of shielded RLC global interconnects are obtained for various international technology roadmap for semiconductors (ITRS) technology nodes.     

Prelayout interconnect yield prediction

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.     

Efficient RC low-power bus encoding methods for crosstalk reduction

In on-chip buses, the RC crosstalk effect leads to serious problems, such as wire propagation delay and dynamic power dissipation. This paper presents two efficient bus-coding methods. The proposed methods simultaneously reduce more dynamic power dissipation and wire propagation delay than existing bus encoding methods. Our methods also reduce more total power consumption than other encoding methods. Simulation results show that the proposed method I reduces coupling activity by 26.7-38.2% and switching activity by 3.7%-7% on 8-bit to 32-bit data buses, respectively. The proposed method II reduces coupling activity by 27.5-39.1% and switching activity by 5.3-9% on 8-bit to 32-bit data buses, respectively. Both the proposed methods reduce dynamic power by 23.9-35.3% on 8-bit to 32-bit data buses and total propagation delay by up to 30.7-44.6% on 32-bit data buses, and eliminate the Type-4 coupling. Our methods also reduce total power consumption by 23.6-33.9%, 23.9-34.3%, and 24.1-34.6% on 8-bit to 32-bit data buses with the 0.18, 0.13, and 0.09 μm technologies, respectively.     

On optimal ordering of signals in parallel wire bundles

Optimal ordering and sizing of wires in a constrained-width interconnect bundle are studied in this paper. It is shown that among all possible orderings of signal wires, a monotonic order of the signals according to their effective driver resistance yields the smallest weighted average delay. Minimizing weighted average delay is a good approximation for MinMax delay optimization. Three variants of monotonic ordering are proven to be optimal, depending on the Miller coupling factors (MCF) ratio between the signals at the sides of the bundle and that of the internal wires. The monotonic order property holds for a very broad range of VLSI circuit settings arising in common design practice. A simple, yet near-optimal, setting of wire widths within the bundle to yield the best average weighted delay is proposed. The theoretical results have been validated by numerical experiments on 65 nm process technology and industrial design data. In all cases the ordering optimization yielded improvement in the range of 10% in wire delay, translated to about 5% improvement in the clock cycle of a high-performance microprocessor implemented in that technology.     

Performance optimization of critical nets through active shielding

We propose the concept of active shields-shields that switch concurrently with a signal wire of interest. Active shields aid signal transitions through the coupling between the signal wire and shields. For RC dominated wires, the active shields switch in the same phase as the signal wire since capacitive coupling is the dominant coupling mechanism. For wires with dominant inductive coupling, active shields switch in the opposite phase of the signal wire. We show that under fixed area and input capacitance constraints, in-phase active shielding outperforms traditional (passive) shielding and wire sizing/spacing techniques for minimizing delays and transition times on RC-dominated wires. For RLC wires, we demonstrate a region of feasibility (in terms of signal wire widths) for which opposite-phase active shielding outperforms the passive shielding technique. Opposite-phase active shielding suppresses ringing behavior to a greater degree than passive shields, providing similar performance to differential signaling while maintaining the simplicity of single ended signaling. The benefits of opposite-phase active shielding as compared to passive shielding are shown in the context of various clock net optimizations where reductions in ringing behavior (up to 4.5X) and transition times (up to 40% reduction) are achieved.     

Wire grid modeling of surfaces

When a surface is numerically modeled with a wire grid, results are sensitive to the wire diameter. It is shown that the best accuracy is obtained when the wire satisfies the "same surface area" rule of thumb, for the canonical problem of scattering (or radiation) from an infinite circular cylinder. It is important to note that wires that are too thick are just as bad as wires that are too thin. It is also shown that the boundary value match between wires is not a reliable check on the validity of farfield results. Finally, data are given on the effect of wire spacing. Results are obtained from exact solutions of both the true problem and the wire grid model, thus isolating the effects of wire grid modeling per se.     

Scattering by imperfectly conducting wires

An integral equation is developed for the current induced in a slender, imperfectly conducting wire of finite length by an incident plane wave. A system of linear equations is generated by enforcing the integral equation at a discrete set of points on the axis of the wire, and these equations are solved to determine the current distribution. The scattered fields and the echo area are then calculated in a straightforward manner. Numerical results are presented for the backscatter echo area of copper, platinum, and bismuth wires at the broadside aspect with lengths up to1.8lambda. These calculations show good agreement with experimental measurements. In addition, graphs are included to show the current distributions on these wires at the second resonance, the echo-area patterns for oblique incidence, and the broadside echo-area curves for perfectly conducting wires and copper wires with lengths up to3.54lambda.     

Wire-Grid Waveguide Bolometers for Multimode Power Measurement

A grid of many fine wires connected in parallel, which completely fills the waveguide cross section, is shown to be useful as a multimode waveguide bolometer. Two such grids with wires that are perpendicular to each other are capable of sampling the power in all modes of propagation below some upper frequency limit determined by the wire spacing. In one case the "wires" consisted of metallized glass fibers, and in a second case they consisted of Wollaston wire wrapped tround supporting glass fibers. The wire-grid configuration which evolved from the thin-film bolometer of the same effective area is more stable and reproducible than the latter.