50 MHz dual-mode buck DC-DC converter

A 50 MHz 1.8/0.9 V dual-mode buck DC-DC converter is proposed in this paper. A dual-mode control for high-frequency DC-DC converter is presented to enhance the conversion efficiency of light-load in this paper. A novel zero-crossing detector is proposed to shut down synchronous rectification transistor NMOS when the inductor crosses zero, which can decrease the power loss caused by reverse current and the trip point is adjusted by regulating IBIAS (BIAS current). A new logic control for pulse-skipping modulation loop is also presented in this paper, which has advantages of simple structure and low power loss. The proposed converter is realized in SMIC 0.18 μm 1-poly 6-metal mixed signal CMOS process. With switching loss, conduction loss and reverse current related loss optimized, an efficiency of 57% is maintained at 10 mA, and a peak efficiency of 71% is measured at nominal operating conditions with a voltage conversion of 1.8 to 0.9 V.     

一种Buck变换器中的误差放大器设计

基于系统稳定性的分析和负载瞬态响应的需求,本文设计了一种用于电流模式恒定导通时间(COT)架构DC-DC降压Buck变换器的高性能误差放大器并提出系统补偿方案。该误差放大器在保证频率特性良好的同时,具备高增益、补偿网络简单的优点。文中对所提出的电路结构以及系统补偿方案进行了详细的说明与理论推导,并使用Simplis软件对系统相位裕度进行仿真,最后基于0.18μm BCD(Bipolar CMOS DMOS)工艺,使用Hspice软件对电路进行了仿真验证。仿真结果表明:电源电压为2.7～5.5 V、输出电压为1.8 V时,系统的相位裕度位于62.5°到69.3°之间,负载瞬态恢复时间最大仅为17.3μs。     

带有高精度片上电流感应器的自适应开关频率降压型DC-DC变换器

本文提出了一种基于电流模式的PWM降压型DC-DC变换器。在高精度片上电流感应器的作用下,当负载不同时自动选择开关频率,提高了系统效率,并获得良好的瞬态响应。电流感应器采用简单的开关技术省去了复杂的运算放大器,但获得了高精度,减少了功率损耗,节省了芯片面积。此外,为了避免启动时的浪涌电流,设计了一种新型的软启动电路。芯片采用了0.5μm标准CMOS工艺,面积3.38mm2,电流感应器的精度可以达到99.5%@200mA,在5-18V的宽输入电压范围内可以输出2A的负载电流。     

Tapped-inductor buck converter for high-step-down DC-DC conversion

The narrow duty cycle in the buck converter limits its application for high-step-down dc-dc conversion. With a simple structure, the tapped-inductor buck converter shows promise for extending the duty cycle. However, the leakage inductance causes a huge turn-off voltage spike across the top switch. Also, the gate drive for the top switch is not simple due to its floating source connection. This paper solves all these problems by modifying the tapped-inductor structure. A simple lossless clamp circuit can effectively clamp the switch turn-off voltage spike and totally recover the leakage energy. Experimental results for 12V-to-1.5V and 48V-to-6V dc-dc conversions show significant improvements in efficiency.     

Boolean-based fractional order SMC for switching systems: application to a DC-DC buck converter

The combination of sliding mode control and fractional order control (FOC) has received a considerable attention in the last years due to the advances and effectiveness of FOC solving robust control problems. This paper collects different methods to apply FOC in sliding mode problems through the use of fractional order surfaces and proposes a direct boolean control (BC) strategy based on this kind of surfaces. The application of BC is novel and takes advantage of avoiding the use of PWM. Simulation results for a DC-DC buck converter application are given to show the goodness of the proposed approach.     

On-chip CMOS current-sensing circuit for DC-DC buck converter

An on-chip CMOS current-sensing circuit for a DC-DC buck converter is presented. The circuit can measure the inductor current through sensing the voltage of the switch node during the converter on-state. By matching the MOSFETs, the achieved sense ratio is almost independent of temperature, model and supply voltage. The proposed circuit is suitable for low power DC-DC applications with high load current.     

A multiple-input DC-DC converter topology

A new topology for multiple energy source conversion is presented. The topology is capable of interfacing sources of different voltage-current characteristics to a common load, while achieving a low part count. A fixed frequency switching strategy is investigated and the resulting operating modes are analyzed. The analysis is verified by experimentation. The results show that the converter is an enabling technology for power diversification and optimization.     

同步降压式DC-DC转换器的稳定性设计

DC-DC转换器因其相比于传统的线性稳压器具有较高的电源转换效率,而被广泛地应用到各种现代电子设备中。同时随着电源整流技术的不断进步,DC-DC转换器也正在从以肖特基二极管作为续流二极管的异步整流模式向同步整流模式转变。同步整流式DC-DC转换器具有极高的电源转换效率(可超过95%),是各种手持设备电源设计的首选。本文从分析同步降压式DC-DC转换器的闭环增益和相位曲线入手,研究了多种条件下如何实现同步降压式DC-DC转换器的稳定性设计。     

Design of high efficiency dual-mode buck DC-DC converter

A buck DC-DC switching regulator with high efficiency is implemented by automatically altering the modulation mode according to load current,and it can operate with an input range of 4.5 to 30 V.At light load current,the converter operates in skip mode.The converter enters PWM mode operation with increasing load current.It reduces the switching loss at light load and standby state,which results in prolonging battery lifetime and stand-by time.Meanwhile, externally adjustable soft-start minimizes the inru...     

一种宽范围可调的小型DC-DC降压变换器

提出了一种小型可调压DC-DC降压变换器的结构。主电路由MOSFET管、电感器及滤波电容器构成。通过PWM波控制,由于PWM波的驱动能力较差,设计驱动电路通过与PWM发生器一同控制MOSFET管的通断。通过改变PWM波的占空比来改变输出电压以达到可调压的目的。该降压变换器设计简单、经济适用、体积较小,输出电压可调。主要由主电路和驱动电路组成。该变换器适用于较低压工作场合,输入电压在5V至20V之间,输出电压在3V至18V之间。对电路的工作原理和结构进行了深入分析,并通过实物制作验证其可行性。     

A novel winding-coupled buck converter for high-frequency, high-step-down DC-DC conversion

This paper analyzes the fundamental limitations of the buck converter for high-frequency, high-step-down dc-dc conversion. Further modification with additional coupled windings in the buck converter yields a novel topology, which significantly improves the efficiency without compromising the transient response. An integrated magnetic structure is proposed for these windings so that the same magnetic cores used in the buck converter can be used here as well. Furthermore, it is easy to implement a lossless clamp circuit to limit the device voltage stress and to recover inductor leakage energy. This new topology is applied for a 12V-to-1.5V/25A voltage regulator module (VRM) design. At a switching frequency of 2MHz, over 80% full-load efficiency is achieved, which is 8% higher than that of the conventional buck converter.     

DC-DC降压变换器的滑模控制研究

为更快获得比较理想的直流输出电压,优化Buck变换器的动态性能,本文分析了一种滑模控制器控制的直流-直流降压变换器,推导了描述降压变换器的动态方程,并设计了滑模控制器。通过MATLAB/Simulink进行仿真,仿真结果表明,基于滑模控制的降压转换器对负载变化和输入电压变化的有效性和鲁棒性。     

用于效率提升的Buck/LDO双模式DC-DC变换器

A novel buck/LDO dual-mode(BLDM) converter using a multiplexing power MOS transistor is proposed,which adaptively switches between buck mode and LDO mode to improve conversion efficiency.The chip was fabricated in a standard 0.35 μm CMOS process.Measurement results show that the peak efficiency is 97%.For the light load operation,the efficiency is improved by 14%.The efficiency keeps higher than 82.5% for the load current of 50 mA without any complex control or extra EMI due to the normal method of pulse frequency modulation(PFM) control used for improving the light load efficiency.It does not cost much extra chip area because no additional regulator PMOS is needed.It is more suitable for noise-restricted systems and battery-powered electronic devices for when battery voltage drops because of long hours of work.     

一种具有动态零点补偿的电流模DC-DC降压型转换器

To achieve fast transient response for a DC-DC buck converter,an adaptive zero compensation circuit is presented.The compensation resistance is dynamically adjusted according to the different output load conditions, and achieves an adequate system phase margin under the different conditions.An improved capacitor multiplier circuit is adopted to realize the minimized compensation capacitance size.In addition,analysis of the small-signal model shows the correctness of the mechanism of the proposed adaptive zero compensation technique.A currentmode DC-DC buck converter with the proposed structure has been implemented in a 0.35μm CMOS process,and the die size is only 800×1040μm~2.The experimental results show that the transient undershoot/overshoot voltage and the recovery times do not exceed 40 mV and 30μs for a load current variation from 100 mA to 1 A.     

Wireless PWM control of a parallel DC-DC buck converter

We demonstrate a new concept for wireless pulse-width modulation (PWM) control of a parallel dc-dc buck converter. It eliminates the need for multiple physical connections of gating/PWM signals among the distributed converter modules. The new scheme relies on radio-frequency (RF) based communication of the PWM control signals from a master to the slave modules. We analyze the system stability and demonstrate the experimental effectiveness of the wireless control scheme for a two-module parallel buck converter for 10-kHz and 20-kHz switching frequencies and for channel lengths of 1.5 and 15ft, respectively. The proposed control concept may lead to easier distributed control implementation of parallel dc-dc converters and distributed power systems, and may lead to redundancy that is achievable using droop method. It may also be used as a backup for wire-based control of parallel converters to provide fault tolerance.     

High-performance error amplifier for fast transient DC-DC converters

A new error amplifier is presented for fast transient response of dc-dc converters. The amplifier has low quiescent current to achieve high power conversion efficiency, but it can supply sufficient current during large-signal operation. Two comparators detect large-signal variations, and turn on extra current supplier if necessary. The amount of extra current is well controlled, so that the system stability can be guaranteed in various operating conditions. The simulation results show that the new error amplifier achieves significant improvement in transient response than the conventional one.     

An improved topology of inductor-switching DC-DC converter

An improved version of an inductor-switching fast-response dc-dc converter is presented that will provide the requirements and features of the new generation of microprocessor and digital systems. Lower output voltage, higher output current, and smaller output voltage ripple requirements have greatly increased the difficulty of the power supply design. To further increase the problem, power-saving "stop-clock" modes of the microprocessor has demanded faster and more stable transient response from the dc-dc converter. A novel method of inductor switching is applied to a dc-dc converter, and it provides the prominent features of current amplification and absorption during the heavy burden of load transients. The design and simulation of the concept is verified by experiment with a 12-V input and 3.3-V/30-A output converter.     

A bidirectional DC-DC converter topology for low power application

This paper presents a bidirectional DC-DC converter for use in low power applications. The proposed topology is based on a half-bridge on the primary and a current-fed push-pull on the secondary side of a high frequency isolation transformer. Achieving bidirectional flow of power using the same power components provides a simple, efficient and galvanically isolated topology that is specially attractive for use in battery charge/discharge circuits in DC UPS. The DC mains (provided by the AC mains), when presented, powers the down stream load converters and the bidirectional converter which essentially operates in the buck mode to charge the battery to a nominal value of 48 V. On failure of the DC mains (derived from the AC mains), the converter operation is comparable to that of a boost and the battery regulates the bus voltage and thereby provides power to the downstream converters. Small signal and steady state analyses are presented for this specific application. The design of a laboratory prototype is included. Experimental results from the prototype, under different operating conditions, validate and evaluate the proposed topology. An efficiency of 86.6% is achieved in the battery charging mode and 90% when the battery provides load power. The converter exhibits good transient response under load variations and switchover from one mode of operation to another     

一种峰值电流型降压DC-DC转换电路的设计

设计了一款基于SMIC 0.35 μmBCD工艺的降压型DC-DC转换芯片,主 要应用于大 功率宽输入范围的电源管理系统。采用峰值电流型PWM控制方式提供优良的负载调整特 性和抗输入电源扰动能力;在电流采样的输出端添加斜坡补偿模块消除峰值电流模式引起 的次谐波振荡问题;设计高增益、大带宽的电压反馈误差放大器以提供大的负载调整率并 提高负载的瞬态响应能力;设计高单位增益带宽的PWM控制器以满足高开关频率工作的 要求,同时提高转换效率。此外,加入了一系列保护模块以维持芯片的正常工作。系统仿 真结果表明:在10 V的输入电压范围内, 稳定输出5.5 V电压,开关频率为330 kHz, 额定输出电流为1.5 A,在输入范围内的转换效率均在80%以上,典型应用下转换效率高 达90%。     

Automotive DC-DC bidirectional converter made with many interleaved buck stages

Interleaving technique is used in some applications due to its advantages regarding filter reduction, dynamic response, and power management. In dual battery system vehicles, the bidirectional dc-dc converter takes advantage of this technique using three-to-five paralleled buck stages. In this paper, we propose the use of a much higher number of phases in parallel together with digital control. It will be shown that this approach opens new possibilities since changes in the technology are possible. Thus, two 1000-W prototypes have been designed using surface mount technology devices (SO-8 transistors). An additional important feature is that due to the accuracy of the digital device [field-programmable gate array (FPGA)], current loops have been eliminated, greatly simplifying the implementation of the control stage.