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磁盘存储系统的高传输密度导致突发错误增多,QC-LDPC码可以作为磁存储系统的纠错编码。研究了构造QC-LDPC码的方法。搭建了磁记录系统模型,使用EPR4和PR4模拟磁记录信道,探讨了不同码率的QC-LDPC码在两种信道下的纠错性能。仿真结果表明QC-LDPC码在两种信道下具有良好的纠错能力。 相似文献
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考虑到围长(girth)对低密度奇偶校验(LDPC)码的影响,提出了一种利用遗传算法构造大girth的准循环LDPC( QC-LDPC)码的新方法。该方法借助于计算机搜索,多次运用遗传算法,分步提高girth,在得到大girth 的同时,构造出具有准循环结构的LDPC码。分析发现,该构造方法的复杂度与码长成线性关系。仿真结果表明:在误码率( BER)为10-6时,新方法构造的QC-LDPC码比基于欧式几何构造方法、Gallager和Mackay构造法分别获得约0.15 dB、0.5 dB和0.2 dB的净编码增益( NCG),且因具有准循环结构更易于存储和硬件实现。 相似文献
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针对具有准循环结构的LDPC码,设计了一种低复杂度译码器。利用校验矩阵的循环特性以及分层迭代的译码算法,对一般的分层迭代架构进行改进,实现了译码器流水线处理,有效的减少迭代时间,提高吞吐量,最后针对码长为1200的LDPC码,基于FPGA平台Kintex7 xc7k325的芯片实现了该架构设计,结果表明,该译码器只消耗了100多个Slices和几块RAM,有效节省了硬件资源,同时译码时间比一般的分层架构减少了2/3左右,吞吐量提高了约2倍,研究成果具有重要的实用价值,可应用于资源有限的低速通信领域。 相似文献
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本文介绍了一种高效、高速哈夫曼解码器的设计与实现。这种解码器的解码算法是建立在一种对哈夫曼树结构的特殊分类的基础上的。这种方法极大地降低了存储哈夫曼表所用的存储器大小,并且提高了查找的速度。 相似文献
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针对随机构造的QC-LDPC码可能在构造中产生会产生短环的情况,提出了添加约束使其没有短环的构造方法,对硬件实现中的采用分层译码算法进行了简要的介绍。实验仿真表明,与传统译码算法相比,分层译码算法具有效率高、延时短及吞吐量大等优点。选用Alter公司的EP3SL340H1152I4器件实现码长为4 096,列重为4,行重为16,码率为3/4的QC-LDPC码的硬件译码算法。译码器在100 MHz的工作频率下,最大迭代次数为5时,吞吐量可以达到157.05 Mbps。 相似文献
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结合杨辉三角的结构形式,基于大衍数列提出了一种列重为3或4的规则准循环低密度奇偶校验(QC-LDPC)码的新构造方法.该方法构造的校验矩阵围长至少为6,码长可灵活变化,并且可节省存储空间.仿真结果表明:在相同的仿真参数下,当误码率(BER)为10-6时,所构造的列重为3的QC-LDPC(1260,620)码的净编码增益(NCG)比二次函数码改善了1 dB左右;列重为4的QC-LDPC(6056,3028)码相对于WMC-OCS、QC-OCS码分别有0.1 dB和0.2 dB的NCG提升. 相似文献
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在电视信号的数字化处理与传输中,复合全电视信号解码是整个处理过程的第一步,它的作用是将复合电视信号解码为数字YUV或数字RGB信号。解码器的质量通常对整个处理系统的性能指标有决定性的作用,并将影响最终的图象质量。本文介绍了一种以Bt812为中心的全数字可编程彩色电视信号解码器的设计。该芯片在图象质量和同步性能方面都有较好的效果,同时具有外围电路简单,编程灵活,应用范围广泛等特点,有广泛的应用前景。 相似文献
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Seok-Jun Lee Shanbhag N.R. Singer A.C. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(8):921-933
Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is recursive and complex, which makes high-speed implementations extremely difficult to realize. In this paper, we present block-interleaved pipelining (BIP) as a new high-throughput technique for MAP decoders. An area-efficient symbol-based BIP MAP decoder architecture is proposed by combining BIP with the well-known look-ahead computation. These architectures are compared with conventional parallel architectures in terms of speed-up, memory and logic complexity, and area. Compared to the parallel architecture, the BIP architecture provides the same speed-up with a reduction in logic complexity by a factor of M, where M is the level of parallelism. The symbol-based architecture provides a speed-up in the range from 1 to 2 with a logic complexity that grows exponentially with M and a state metric storage requirement that is reduced by a factor of M as compared to a parallel architecture. The symbol-based BIP architecture provides speed-up in the range M to 2M with an exponentially higher logic complexity and a reduced memory complexity compared to a parallel architecture. These high-throughput architectures are synthesized in a 2.5-V 0.25-/spl mu/m CMOS standard cell library and post-layout simulations are conducted. For turbo decoder applications, we find that the BIP architecture provides a throughput gain of 1.96 at the cost of 63% area overhead. For turbo equalizer applications, the symbol-based BIP architecture enables us to achieve a throughput gain of 1.79 with an area savings of 25%. 相似文献
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多码率LDPC码高速译码器的设计与实现 总被引:2,自引:0,他引:2
低密度奇偶校验码(LDPC码)以其接近香浓极限的性能得到了广泛的应用.如何在.FPGA上实现多码率LDPC码的高速译码,则是LDPC码应用的一个焦点.本文介绍了一种多码率LDPC码及其简化的和积译码算法;设计了这种多码率LDPC码的高速译码器,该译码器拥有半并行的运算结构和不同码率码共用相同的存储单元的存储资源利用结构,并以和算法与积算法功能单元同时工作的机制交替完成对两个码字的译码,提高了资源利用率和译码速率.最后,本文采用该结构在FPGA平台上实现了码长8064比特码率7/8、6/8、5/8、4/8、3/8五个码率的多码率LDPC码译码器.测试结果表明,译码器的有效符号速率达到200Mbps. 相似文献
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针对部分并行结构的准循环低密度校验(QC-LDPC)码译码器,提出了一种将译码准码字存储在信道信息和外信息存储块中的高效存储方法,该方法不需要额外的存储块来存储译码准码字,能够减少译码器实验所需的存储资源数量,并且有效降低了译码电路的布线复杂度.在Xilinx XC2V6000-5ff1152 FPGA上的实验结果表明,提出的QC-LDPC码译码器设计方法能够在降低系统的BRAM资源需求量的同时有效地提高系统的运行频率和译码吞吐量. 相似文献
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This paper presents a memory efficient architecture of layered decoder for the dual-rate LDPC codes in the China Multimedia Mobile Broadcasting (CMMB) system. An efficient scheme for reducing the memory block number is proposed to increase the memory usage efficiency, so that the quantity of memory bits, decoder area and power consumption is significantly reduced. At the same time, the memory structure keeps the “one cycle one layer access” timing schedule to achieve high decoding throughput. Furthermore, the early termination strategy is employed to further increase the throughput; a non-uniform quantization scheme and an area efficient calculation module are developed to further improve the memory efficiency and hardware resource efficiency, respectively. By using SMIC 130 nm 1P7M CMOS process, the decoder is implemented and the core area is 5.29 mm2. The total memory bits consumption is only 130.5 K which consumes 2.53 mm2 memory area. 相似文献
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Fei Sun Tong Zhang 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(9):1013-1022
Limited search trellis decoding algorithms have great potentials of realizing low power due to their largely reduced computational complexity compared with the widely used Viterbi algorithm. However, because of the lack of operational parallelism and regularity in their original formulations, the limited search decoding algorithms have been traditionally ruled out for applications demanding very high throughput. We believe that, through appropriate algorithm and hardware architecture co-design, certain limited search trellis decoding algorithms can become serious competitors to the Viterbi algorithm for high-throughout applications. Focusing on the well-known T-algorithm, this paper presents techniques at the algorithm and VLSI architecture levels to design fully parallel T-algorithm limited search trellis decoders. We first develop a modified T-algorithm, called SPEC-T, to improve the algorithmic parallelism. Then, based on the conventional state-parallel register exchange Viterbi decoder, we develop a parallel SPEC-T decoder architecture that can effectively transform the reduced computational complexity at the algorithm level to the reduced switching activities in the hardware. We demonstrate the effectiveness of the SPEC-T design solution in the context of convolutional code decoding. Compared with state-parallel register exchange Viterbi decoders, the SPEC-T convolutional code decoders can achieve almost the same throughput and decoding performance, while realizing up to 56% power savings. For the first time, this work provides an approach to exploit the low power potential of the T-algorithm in very high throughput applications. 相似文献
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一种准循环LDPC解码器的设计与实现 总被引:5,自引:5,他引:0
面向准循环LDPC码的硬件实现,定点分析了各种解码算法的解码性能,偏移量最小和(OMS)算法具备较高解码性能和实现复杂度低的特点.提出一种基于部分并行方式的准循环LDPC解码器结构,在FPGA上利用该结构成功实现了WiMAX标准中的LDPC解码器.FPGA验证结果表明,采用该结构的解码器性能优良,实现复杂度低,数据吞吐率高. 相似文献
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码长连续变化的QC-LDPC码的设计 总被引:2,自引:0,他引:2
该文基于有限多项式环的理论,提出了码长连续变化的准循环低密度奇偶校验(Quasi-Cyclic Low Density Parity Check, QC-LDPC)码的设计方法。当有限环基数大于某个门限值时,在此环内通过一定规则选择参数生成移位项,利用它们构造出的校验矩阵均可以达到较大的圈长(girth)值。在设计中,有限环基数为连续的整数,且基数与码长呈线性关系,因此能够在girth值不变的前提下实现码长的连续变化。该文分析并证明了该构造方法大大增加了可用的高性能QC-LDPC码数量,更好地服务于自适应链路系统。 相似文献
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FMO编码以其便于位同步提取、频谱带宽较窄、实现电路简单而在ETC中得到广泛的应用,线路FMO解码模块是ETC系统基带电路重要组成部分,本文基于ETC系统中车载单元(On board unit,OBU)与路边单元(Road side unit,RSU)之间的短距离双向通信,以提高FMO解码速度的目的,根据FMO编码原则,在FPGA软件环境下用高级硬件描述语言VHDL实现FMO解码器设计,给出程序代码,在Quartus Ⅱ环境下仿真,并通过逻辑分析仪观察波形.同等功能下,解码时间是图形输入法的五分之一. 相似文献