A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K×8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8-μm CMOS process technology. Standby power is 25 μW, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8×8.5-μm² cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size is 7.6×12.4 mm²     

An 18-ns 1-Mbit CMOS SRAM

A 1-Mb (256 K×4 b) CMOS static random-access memory with a high-resistivity load cell was developed with 0.7-μm CMOS process technology. This SRAM achieved a high-speed access of 18 ns. The SRAM uses a three-phase back-bias generator, a bus level-equalizing circuit and a four-stage sense amplifier. A small 4.8×8.5-μm² cell was realized by the use of a triple-polysilicon structure. The grounded second-polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size measures 7.5×12 mm²     

DRAM macros for ASIC chips

DRAM macros in 4-Mb (0.8-μm) and 16-Mb (0.5-μm) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT cell) DRAM products. It is shown that the trench cells with capacitor plates by the grounded substrate are ideal structures as embedded DRAM's. The trench cells built entirely under the silicon surface allow cost effective DRAM and CMOS logic merged process technologies. In the 0.8-μm rule, the DRAM macro has a 32-K×9-b configuration in a silicon area of 1.7×5.0 mm² . It achieves a 27-ns access and a 50-ns cycle times. The other DRAM macro in the 0.5-μm technology is organized in 64 K×18 b. It has a macro area of 2.1×4.9 mm and demonstrated a 23-ns access and a 40-ns cycle times. Small densities and multiple bit data configurations provide a flexibility to ASIC designs and a wide variety of application capabilities. Multiple uses of the DRAM macros bring significant performance leverages to ASIC chips because of the wide data bus and the fast access and cycle times. A data rate more than 1.3 Gb/s is possible by a single chip. Some examples of actual DRAM macro embedded ASIC chips are shown     

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-linearchitecture

A 16-Mb dynamic RAM has been designed and fabricated using 0.5-μm CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3-μm² in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4×17.38 (93.85) mm² to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time     

A 20 K CMOS array with 200-ps gate delay

A 20 K NAND2 equivalent CMOS gate array prototype with 0.5-μm channel length FETs is described. The 7.5×7.5-mm chip is designed for high performance with 200-ps gate delay. Large macros such as a 32-b RISC (reduced instruction-set computer) processor and 128×8 SRAM (static random-access memory) have been implemented with automatic placement and wiring tools. Their respective predicted performances of 17-ns cycle and 6.1-ns access time have been verified. This confirms that the speed of complex functions in half-micrometer-channel-length CMOS technology is getting close to the speed achieved by current bipolar hardware     

A 7.5-ns 32 K×8 CMOS SRAM

A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm² and the chip size is 4.38×9.47 mm ²     

A 15-ns 1-Mbit CMOS SRAM

A 1-Mb CMOS static RAM with a 256 K word×4-bit configuration has been developed. The RAM was fabricated using 0.8-μm double-poly and double-aluminum twin-well CMOS technology. A small cell size of 5.2 μm×8.5 μm and a chip size of 6.15 mm×15.21 mm have been achieved. A fast address access time of 15 ns was achieved using novel circuit techniques: a PMOS-load decoder and a three-stage dynamic gain control sense amplifier combined with an equalization technique and feedback capacitances. A low active current of 50 mA at 20 MHz and low standby currents of 15 mA (TTL) and 2 μA (CMOS) were also attained     

A 12-ns ECL I/O 256 K×1-bit SRAM using a 1-μm BiCMOStechnology

An ECL (emitter-coupled-logic) I/O 256K×1-bit SRAM (static random-access memory) has been developed using a 1-μm BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8-μm CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1     

A 55-ns 16-Mb DRAM with built-in self-test function usingmicroprogram ROM

A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55-μm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm² chip area was attained by implementing 4.05-μm² storage cells. The installed ROM was composed of 18 words×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm² and the area overhead is about 1%, it proves to be promising for large-scale DRAMs     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

An 11000-fuse electrically erasable programmable logic device(EEPLD) with an extended macrocell

A high-performance electrically erasable programmable logic device (EEPLD) has been designed and fabricated using a 1.5-μm n-well CMOS technology. The chip has 11040 fuses which are used not only in the logic array but also in the input/output macrocell. Typical access time for the nonregistered version is 35 ns with a power dissipation of 450 mW. There are 16 input/output macrocells which are architecturally defined by 128 electrically programmable fuses. Die size is 130×230 mils     

Circuit techniques for CMOS low-power high-performance multipliers

In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-μm CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16×16)-b multiplier using the Booth algorithm, a (6×6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6×6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS     

8-ns CMOS 64 K×4 and 256 K×1 SRAMs

SRAMs (static random-access memory) with a 64 K×4 and 256 K×1 structure and with 8-ns access time have been developed on a 1.0-μm CMOS process. Circuits are designed with source-coupling techniques to achieve high speed with small signal swings, using only CMOS devices. A metal option permits selection of the 64 K×4 or 256 K×1 configuration. The same core architecture has also been used to generate ×8 and ×9 designs. An output-enable (OE) version achieves 3-ns response time. As system speeds have recently increased toward 100-MHz operation, the need for address transition detection (ATD) has diminished as a means for improving the SRAM speed/power ratio. This trend in SRAM design stems mainly from the fact that AC current becomes the most significant fraction of the total current. Accordingly, the design described here employs a purely static path through the entire SRAM, with no requirement of ATD at any point. The resulting DC current is countered with a combined strategy of array subdivision, small-signal techniques, and active preamplification at key points in the data path     

A 32×32-bit multiplier using multiple-valued MOS current-modecircuits

A 32×32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2-μm CMOS technology. For the multiplier based on the radix-4 signed-digit number system, 32×32-bit two's complement multiplication can be performed with only three-stage signed-digit full adders using a binary-tree addition scheme. The chip contains about 23600 transistors and the effective multiplier size is about 3.2×5.2 mm², which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported     

A 33-ns 64-Mb DRAM

A 64-Mb CMOS dynamic RAM (DRAM) measuring 176.4 mm² has been fabricated using a 0.4-μm N-substrate triple-well CMOS, double-poly, double-polycide, double-metal process technology. The asymmetrical stacked-trench capacitor (AST) cells, 0.9 μm×1.7 μm each, are laid out in a PMOS centered interdigitated twisted bit-line (PCITBL) scheme that achieves both low noise and high packing density. Three circuit techniques were developed to meet high-speed requirements. Using the preboosted word-line drive-line technique, a bypassed sense-amplifier drive-line scheme, and a quasi-static data transfer technique, a typical RAS access time of 33 ns and a typical column address access time of 15 ns have been achieved     

A 14-ns 1-Mbit CMOS SRAM with variable bit organization

The authors describe a 14-ns 1-Mb CMOS SRAM (static random-access memory) with both 1M word×1-b and 256 K word×4-b organizations. The desired organization is selected by forcing the state of an external pin. The fast access time is achieved by the use of a shorter divided-word-line (DWL) structure, a highly sensitive sense amplifier, a gate-controlled data-bus driver, and a dual-level precharging technique. The 0.7-μm double-aluminum and triple-polysilicon process technology with trench isolation offers a memory cell size of 41.6 μm² and a chip size of 86.6 mm ². The variable bit-organization function reduces the testing time while keeping the measurement accuracy of the access times     

The twin-transistor noise-tolerant dynamic circuit technique

This paper describes a new circuit technique for designing noise-tolerant dynamic logic. It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design. In a 0.35-μm CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise immunity of 1.8×(for an AND gate) and 2.5×(for an adder carry chain) over domino at the same speed. A multiply-accumulate circuit has been designed and fabricated using a 0.35-μm process to verify this technique. Experimental results indicate that the proposed technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4x) with only a modest increase in power dissipation (15%) and no loss in throughput     

A 4-ns 4K×1-bit two-port BiCMOS SRAM

The authors introduce a two-port BiCMOS static random-access memory (SRAM) cell that combines ECL-level word-line voltage swings and emitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAMs while preserving the high density and low power of CMOS memory arrays. The memory can be read and written simultaneously and is therefore well-suited to applications such as high-speed caches and video memories. A read access time of 3.8 ns at a power dissipation of 520 mW has been achieved in an experimental 4K×1-bit two-port memory integrated in a 1.5-μm 5-GHz BiCMOS technology. The access time in this prototype design is nearly temperature-insensitive, increasing to only 4 ns at a case temperature of 100°C     

A 2-ns detecting time, 2-μm CMOS built-in current sensingcircuit

Built-in current testing is known to enhance the defect coverage in CMOS VLSI. An experimental CMOS chip containing a high-speed built-in current sensing (BICS) circuit design is described. This chip has been fabricated through MOSIS 2-μm p-well CMOS technology. The power bus current of an 8×8 parallel multiplier is monitored. This BICS detects all implanted short-circuit defects and some implanted open-circuit defects at a clock speed of 30 MHz (limited by the test setup). SPICE3 simulations indicate a defect detection time of about 2 ns     

A 23-ns 4-Mb CMOS SRAM with 0.2-μA standby current

A 4-Mb CMOS SRAM having 0.2-μA standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power-reduction characteristics at a low operating cycle time without access delay. A 0.5-μm CMOS, four-level poly, two-level metal technology with a polysilicon PMOS load memory cell, yielded a small cell area of 17 μm² and the very small standby current. A quadruple-array, word-decoder architecture allowed a small chip area of 122 mm²