共查询到20条相似文献,搜索用时 15 毫秒
1.
A high-speed rail-to-rail output buffer with push–pull dual-path and dynamic-bias for LCD driver ICs
The design of a low-power high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs
is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB
output stage and auxiliary output stage at the same time; the proposed output buffer thus has a push–pull dual-path function
for high-speed operation. Since a conventional class-AB output stage requires two bias voltages, the proposed output buffer
provides two dynamic bias voltages to increase the transient response of the class-AB output stage. The two dynamic biases
use only two transistors and do not increase the quiescent current. The proposed output buffer is implemented on standard
0.35 μm CMOS 2-poly 4-metal process technology and simulated using HSPICE. The power consumption is 23.1 μW, with settling
times of 0.7 and 0.68 μs for rising and falling edges, respectively, under a 1000 pF load. The active area of the output buffer
amplifier is only 48 × 48 μm2. 相似文献
2.
To achieve low voltage high drivingcapability with quiescent current control, a class-AB CMOS buffer amplifier usingimproved quasi-complementary output stage and error amplifiers with adaptive loadsis developed. Improved quasi-complementary output stage enables it more suitablefor low voltage applications, while adaptive load in error amplifier is used toincrease the driving capability and reduce the sensitivity of the quiescentcurrent to fabrication process variation. The circuit has been fabricated in 0.8μm CMOS process. With 300 Ω load in a ±1.5 V supply, its outputswing is 2.42 V. The mean value of quiescent current for eight samples is 204μA, with the worst deviation of 17%. 相似文献
3.
Davide Marano Gaetano Palumbo Salvatore Pennisi 《Analog Integrated Circuits and Signal Processing》2010,65(2):289-298
The present paper addresses a new compact low-power high-speed output buffer amplifier topology for large-size liquid crystal
display applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static
operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited
power consumption by simultaneously exploiting the push–pull output sections of two basic complementary-type input amplifiers
to realize a dual-path push–pull operation of the output stage. An auxiliary biasing network integrated in the input differential
stage allows the quiescent bias conditions of the class-AB output stage to be inherently controlled without additional current
dissipation. Post-layout simulation results confirm that the proposed amplifier can drive a 1-nF column line load within a
0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current. Monte Carlo simulations
are finally carried out, showing a good degree of robustness of the proposed output buffer against process and mismatch variations. 相似文献
4.
《Solid-State Circuits, IEEE Journal of》1976,11(2):323-328
The design of a monolithic operational amplifier, which combines a large bandwidth and a high output current, is described. The output stage is equipped with n-p-n transistors only, biased in class-AB by an internal common-mode feedback loop. The intermediate stage consists of a unity-current-gain split-frequency-band voltage level shift. An integrated version, intended for driving 50-/spl Omega/ coaxial line systems, achieves a bandwidth of 25 MHz and 100-mA output current. The principle described provides the possibility for achieving higher output currents. 相似文献
5.
Chih-Wen Lu Yen-Chung Huang 《Electronics letters》2004,40(1):1-2
A 1.5 V large-driving class-AB buffer amplifier with quiescent current control suitable for output driver application is proposed. An experimental prototype buffer demonstrated that the circuit draws only 80 /spl mu/A static current, and exhibited the rise time of 0.4 /spl mu/s and fall time of 1 /spl mu/s under a 100 /spl Omega///150 pF load. 相似文献
6.
Chih-Wen Lu 《Solid-State Circuits, IEEE Journal of》2004,39(11):1938-1947
A high-speed driving scheme and a compact high-speed low-power rail-to-rail class-B buffer amplifier, which are suitable for small- and large-size liquid crystal display applications, are proposed. The driving scheme incorporates two output driving stages in which the output of the first output driving stage is connected to the inverting input and that of the second driving stage is connected to the capacitive load. A compensation resistor is connected between the two output stages for stability. The second output stage is used to improve the slew rate and the settling time. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators to sense the transients of the input to turn on the output stages, which are statically off in the stable state. This increases the speed of the circuit without increasing static power consumption too much. A rail-to-rail folded-cascode differential amplifier is used to amplify the input signal difference and supply the bias voltages for the second stage. An experimental prototype output buffer implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the circuit draws only 7-/spl mu/A static current and exhibits the settling times of 2.7 /spl mu/s for rising and 2.9 /spl mu/s for falling edges for a voltage swing of 3.3 V under a 600-pF capacitance load with a power supply of 3.3 V. The active area of this buffer is only 46.5/spl times/57/spl mu/m/sup 2/. 相似文献
7.
A monolithic quad audio power amplifier which reduces power dissipation by 45% with a music signal compared to a standard class-AB amplifier is described. A new two-stage operational amplifier, capable of providing high output current, is used for each one of eight power amplifiers. In a bridge configuration, a common-loop mode control is performed exploiting a sample-and-hold circuit. A multipower bipolar-CMOS-DMOS (BCD) technology is employed with a push-pull rail-to-rail output stage and a low-loss power switch. Experimental results are presented 相似文献
8.
9.
Jeongjin Roh 《Analog Integrated Circuits and Signal Processing》2006,47(2):225-228
High-performance operational transconductance amplifier (OTA) is designed for switched-capacitor applications. Without using
a cascoded output stage, which limits the voltage swing, the output resistance is significantly increased for high DC gain
by accurately controlling the output current. Also, the output stage has class-AB operation, so the overall power efficiency
is improved. With significantly low quiescent current, the presented new OTA achieves higher DC gain than conventional OTAs.
Theoretical analysis and HSPICE simulations prove the performance of the new OTA. 相似文献
10.
Chih-Wen Lu Chung Len Lee 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2002,10(2):163-168
A low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer circuit, which is suitable for flat-panel display application, is proposed. The circuit employs an elegant comparator to sense the transients of the input to turn on charging/discharging transistors, thus draws little current during static, but has an improved driving capability during transients. It is demonstrated in a 0.6 μm CMOS technology 相似文献
11.
A. van Staveren G. L. E. Monna C. J. M. Verhoeven A. H. M. van Roermund 《Analog Integrated Circuits and Signal Processing》1999,20(1):63-75
The design and the measurement results are presented of a low-voltage (1 V) class-AB negative-feedback output amplifier. The amplifier is designed for use in a single-chip LW receiver, which can be put completely in the ear, supplied by a 1 V power supply and is capable of driving a load with an impedance of 30 . The maximum output current of the amplifier is approximately 2.5 mA and its quiescent current is approximately 100 A. This high efficiency is obtained by means of biasing two of the three amplifying stages in class-AB operation. With the aid of negative feedback, the total harmonic distortion for a single 1 kHz tone at 1 mA level is kept below 1%. The output amplifier is integrated in a bipolar process which has vertical NPN transistors with a maximum f
T
of 5 GHz and lateral PNP transistors with a maximum f
T
of 20 MHz. 相似文献
12.
A new high-slew-rate CMOS buffer amplifier consuming a very small quiescent current is proposed. This buffer amplifier recursively copies the output driving current and increases the tail current of the input differential pair during slewing. Since the proposed buffer has a possible slew rate higher than 10 V//spl mu/s for a load capacitance of 1 nF almost independently of static currents as low as 1 /spl mu/A, this buffer amplifier is promising for column driver ICs of flat panel displays that require low static power consumption, high current driving capabilities, and small silicon areas. 相似文献
13.
Pang-Cheng Yu Jiin-Chuan Wu 《Solid-State Circuits, IEEE Journal of》1999,34(1):116-119
Due to the large number of output buffers on a column driver chip of a flat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, large output swing, and wide operating voltage range class-B output buffer amplifier for driving the large column line capacitance in a flat-panel display. A comparator is used in the negative feedback path to eliminate quiescent current in the output stage. The proposed output buffer circuit was implemented in a 0.8 μm CMOS process. Its output voltage swing is from 1 V to the supply voltage. With 5 V supply and 600 pF load, the maximum tracking error is ±7 mV. The measured static current is 24 μA. The settling time for 4 V swing to within 0.2% is 8 μs, which is more than adequate for driving 1280×1024 pixels liquid crystal displays with 86 Hz frame rate and 256 gray levels in each color 相似文献
14.
W. C. M. Renirie K. J. De Langen J. H. Huijsing 《Analog Integrated Circuits and Signal Processing》1995,8(1):37-48
A new family of class-AB control circuits for bipolar rail-to-rail output stages of operational amplifiers is presented. Step by step, we report the development of five simple class-AB control circuits showing the advantages of using parallel feedforward. The circuits have been designed in such a way that temperature, supply voltage and process parameters have little influence. To test the output stages, one of them has been implemented in a very simple two-stage operational amplifier on a semi-custom chip. Measurements show a bandwidth of 2.5 MHz, a gain of 40 dB, a quiescent current of 23µA and a maximum output current of 250µA. Simulation results of three other simple operational amplifiers with the new class-AB control circuits are shown, which have a higher gain and maximum output current. 相似文献
15.
正A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers.The enhancer utilizes the class-AB input stage to improve current efficiency,while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier.During the slewing period,the enhancer detects input differential voltage of the amplifier,and produces external enhancement currents for the amplifier,driving load capacitors to charge/discharge faster.Simulation results show that,fora large input step,the enhancerreduces settling time by nearly 50%.When the circuit is employed in a sample-and-hold circuit,it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB.The proposed circuit is very suitable to operate under a low voltage(1.2 V or below) with a standby current of 200μA. 相似文献
16.
设计了一种工作电压为3V恒跨导满幅CMOS运算放大器,针对轨对轨输入级中存在的跨导不恒定和简单AB类输出级性能偏差这2个问题,提出了利用最小电流选择电路来稳定输入级的总跨导;浮动电流源控制的无截止前馈AB类输出级实现了运放的满幅输出,同时减小了交越失真。该电路通过HSpice进行仿真验证,在0~3V输入共模范围内,输入级跨导的变化小于3.3%,开环增益为93dB,单位增益带宽为8MHz,相位裕量为66°。 相似文献
17.
《Microwave Theory and Techniques》2008,56(1):77-87
The class-AB/F power amplifier (PA), a multimode PA, which can operate at both class-AB and class-F modes, is analyzed and compared with the conventional class-F and class-AB PAs. The open-circuited third harmonic control circuit enhances the efficiency of the PA without deteriorating the linearity of class-AB mode of the PA. The voltage and current waveforms are simulated to evaluate the appropriate operation for the modes. To demonstrate the multimode PA, the PA is implemented using an InGaP/GaAs HBT process and it is tested with reverse-link IS-95A code division multiple access (CDMA) and PCS1900 global system for mobile communications signals in the personal communications service band. The class-AB operation for a CDMA signal delivers a power-added efficiency (PAE) of 38.9% and an adjacent channel power ratio of 49.5 and 56.5 dBc at the offset of 1.25 and 2.25 MHz, respectively, at the output power of 28 dBm. The maximum PAE of 64.7% under the class-F operation is measured at 32.5-dBm output power for a GSM signal. The class-AB/F PA is a good candidate for the multimode PA of next-generation wireless communication systems. 相似文献
18.
Carrillo J.M. Torelli G. Perez-Aloe R. Duque-Carrillo J.F. 《Solid-State Circuits, IEEE Journal of》2007,42(3):508-517
This paper introduces a CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments. The approach is based on a bulk-driven input stage with extended input common-mode voltage range, in which the effective input transconductance is enhanced by means of a partial positive feedback loop. As a result, a gain and gain-bandwidth product performance similar to that of an amplifier using a gate-driven approach is obtained. Output rail-to-rail operation is achieved by means of a push-pull stage, which is biased in class-AB by using a static feedback loop, thus avoiding frequency limitations inherent in dynamic-feedback tuning schemes. The proposed two-stage operational amplifier was designed to operate with a 1-V supply, and a test chip prototype was fabricated in 0.35-mum standard CMOS technology. The experimental performance features an open-loop DC gain higher than 76 dB and a closed-loop unity-gain bandwidth above 8 MHz when a 1-MOmegapar17-pF load is connected to the amplifier output 相似文献
19.
20.
本文提出了一种低压工作的轨到轨输入/输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO.6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明:当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87.7dB,功耗为579uw,单位增益带宽为3.3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53.2dB。 相似文献