Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than /spl omega/W; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.     

Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits

In this paper, the effects of energy quantization on different single-electron transistor (SET) circuits (logic inverter, current-biased circuits, and hybrid MOS-SET circuits) are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantization mainly increases the Coulomb blockade area and Coulomb blockade oscillation periodicity, and thus, affects the SET circuit performance. A new model for the noise margin of the SET inverter is proposed, which includes the energy quantization effects. Using the noise margin as a metric, the robustness of the SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as “ quantization threshold”) that an SET inverter can withstand before its noise margin falls below a specified tolerance level. The effects of energy quantization are further studied for the current-biased negative differential resistance (NDR) circuit and hybrid SETMOS circuit. A new model for the conductance of NDR characteristics is also formulated that explains the energy quantization effects.      

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.     

一种SETMOS二阶带通滤波器设计实现

单电子晶体管（SET）作为一种纳电子器件有着较大的优势,将SET与纳米MOS混合构成的器件（SETMOS）是目前研究的热点之一。SETMOS作为一种新的混合器件,在结合了两者优点的同时,具有与SET一样的库仑振荡特性和MOS高增益等特性。文章基于一种sETM0s混合结构的电压电流特性的数学模型,设计并实现了一种SETMOS二阶带通滤波器,阐述了这种SETMOS带通滤波器的结构、工作条件、性能、参数和特点,并用PSpice对其传输特性进行了仿真验证,结果证明,SETMOS在其通带范围内具有良好的带通幅频特性,且具有低电压、低功耗和高频的特点。     

2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

MOS bulk transistor is reaching its limits: sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage (VT) and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Fully depleted devices are mandatory to continue the technology roadmap. FDSOI technology relies on a thin layer of silicon that is over a buried oxide (BOx). Called ultra thin body and buried oxide (UTBB) transistor, FDSOI transistors correspond to a simple evolution from conventional MOS bulk transistor. The capability to bias the back-gate allows us to implement calibration techniques without adding transistors in critical blocks. We have illustrated this technique on a very low power voltage-controlled oscillator (VCO) based on a ring oscillator (RO) designed in 28 nm FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient back-gate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise. We will present the reasons which led us to use the FDSOI technology to reach the specifications of this PLL. The VCRO exhibits a 0.8 mW power consumption, with a phase noise about --94 dBc/Hz@1 MHz.     

A novel SET/MOSFET hybrid static memory cell design

In this paper, a single electron transistor (SET)/metal-oxide-semiconductor field effect transistor (MOSFET)-based static memory cell is proposed. The negative differential conductance (NDC) characteristics of the SET block help us establish the static memory cell circuits more compactly than those in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks exhibiting the NDC. The peak-to-valley current ratio of the SET block is above four with C/sub G/=5.4C/sub T/ (C/sub T/=0.1 aF) at T=77K. The read and write operations of the proposed memory cell were validated with SET/MOSFET hybrid simulations at T=77 K. Even though the fabrication process that integrates MOSFET devices and SET blocks with NDC is not yet available, these results suggest that the proposed SET/MOSFET hybrid static memory cell is suitable for a high-density memory system.     

Direct, fast, and accurate measurement of VTand K of an MOS transistor using a VT-siftcircuit

Based on a V_T-sift circuit, a new characterization technique is presented with which the value of both K, the transconductance constant, and V_T, the device threshold voltage, of an MOS transistor can be measured directly, obtained from the drain current of the device to be tested and the voltage difference between the output and input nodes of the V _T-sift circuit, respectively. The proposed method has been verified experimentally and compared advantageously with the commonly used linear regression technique in transistor characterization and wafer manufacturing. An additional application field of the V _T-sift circuit is temperature compensation of analog circuits     

Impact of Key Circuit Parameters on Signal-to-Noise Ratio Characteristics for the Radio Frequency Single-Electron Transistors

Hybrid simulation was performed to analyze the response of the real-time reflection-type radio frequency single-electron transistor (RF-SET) measurement system. A compact and physically-based analytical SET model, which was validated with a Monte Carlo simulator, was used to simulate the SET characteristics, while SPICE equivalent circuits were implemented to simulate all other components of the RF-SET measurement system. The impact of various key parameters on the RF-SET response was demonstrated for a carrier frequency much less than I/e ( is the typical current through the SET). It was revealed that an inevitable feed-through loss between the tank circuit and the cryogenic amplifier, and high-frequency parasitics of the inductor degrade the RF-SET performance significantly. As such, they have to be optimized to experimentally realize the shot-noise-limited charge sensitivity.     

Advances in the modeling of single electron transistors for the design of integrated circuit

Single electron transistor (SET) has become a promising candidate for the key device of logic circuit in the near future. The advances of recent 5 years in the modeling of SETs are reviewed for the simulation of SET/hybrid CMOS-SET integrated circuit. Three dominating SET models, Monte Carlo model, master equation model and macro model, are analyzed, tested and compared on their principles, characteristics, applicability and development trend. The Monte Carlo model is suitable for SET structure research and simulation of small scale SET circuit, while the analytical model based on combination with master equation and macro model is suitable to simulate the SET circuit at balanceable efficiency and accuracy.     

High-frequency time-ratio control with insulated and isolated inputs

Fast-responding amplifiers are needed in many industrial and defense systems. Systems using power amplifiers with one to 1000 watts of output dc power require high performance. The requirements often include high efficiency, light weight, compactness, high reliability, economy, and simplicity, along with fast response and insulated multiple inputs. These performances are required in applications such as controls for high-power inverters and converters, motors, generators, light, heat, dc-to-ac inverters, power supplies, servo systems, etc. This paper presents a transistor-magnetic power amplifier with multiple insulated and isolated inputs (Fig. 1) with characteristics in Fig. 2. The technique of time-ratio control [1] is used to provide light weight, compactness, high efficiency, and high reliability. High-speed power transistors (0.1 μs) combined with a tunnel diode circuit permit high chopping frequency (50 kc). The base current of the power transistor is switched in-less than 0.02 μs. Insulated and isolated inputs are provided by a small saturable transformer the size of a TO-5 transistor case. Transistor inputs are used on the saturable transformer. Germanium power transistors (such as 2N1907) are used to provide economy, but silicon transistors can be used for applications at high ambient temperature. The circuit of Fig. 1 is used to fire controlled rectifiers for inverters and converters. A pulse transformer in series with a resistor replaces the load of Fig. 1 when needed in firing circuits. A simple time-ratio control (TRC) circuit is presented that controls the output [Fig. 2(a)] by varying the chopping frequency from 50 kc to 5 kc. The multiple inputs are illustrated. A constant frequency (50 kc) TRC is presented that controls load voltage from zero to the supply voltage [Fig. 2(b)]. The output responds to the control signal in 40 μs. The tunnel diode switching circuit is also presented.     

Tunable ferroelectric capacitor-based voltage-controlled oscillator

Ferroelectric capacitors made from Ba(1-0.5)Sr0.5TiO3 (BST) are applied as varactors in tunable, high-frequency circuit applications. In this context, a voltage-controlled oscillator (VCO) has been designed and implemented using discrete RF bipolar junction transistor (BJTs) and tunable ferroelectric capacitor. The designed VCO has a tuning range from 205 MHz to 216.3 MHz with a power dissipation of 5.1 mW. The measured phase noise is -90 dBc/Hz at 100 kHz and -140 dBc/Hz at 1 MHz offset.     

Measuring and fitting the MOS transistor at high frequencies

A novel small-signal model of a MOS transistor is presented, which is valid at frequencies around the unity gain frequency. As a major advantage compared with earlier models, this novel model takes into account the nonquasistatic and transmission-line effects of the transistor. By using S-parameter measurements, computer-controlled calibration techniques of the test setup and network analyzer, mathematical transformations and fit routines, all the AC parameters can be extracted from the measured data. The obtained model parameters are used in the design of a high-frequency circuit to prove the validity of the model as well as the measurement method     

Design of a Robust Analog-to-Digital Converter Based on Complementary SET/CMOS Hybrid Amplifier

As a solution to the high speed, ultralow power, and extremely compact ADC circuit block, a complementary single-electron transistor (SET)/CMOS hybrid amplifier-based analog-to-digital converter (ADC) is proposed. It is implemented with a physics-based SPICE model including nonideal effects in real Si-based SET_s such as the tunnel barrier lowering effect, parasitic MOSFET_s operation, and the phase shift of Coulomb oscillation by the bias of a gate other than a main control gate. Its core scheme is the combination of both the amplification of SET current by MOSFET_s and the suppression of a Coulomb blockade oscillation valley current by the differential amplification. In addition, the transient operation of SET/CMOS hybrid circuit-based ADC_s fully accounting for nonideal effects of real SET_s is successfully demonstrated for the first time. Compared with the previous SET-based ADC_s, our ADC makes features of the immunity to nonideal effects, large voltage swing of the output signal, and high load drivability.     

Optimization of an ultra low-phase noise sapphire--SiGe HBT oscillator using nonlinear CAD

In this paper, the electrical and noise performances of a 0.8 /spl mu/m silicon germanium (SiGe) transistor optimized for the design of low phase-noise circuits are described. A nonlinear model developed for the transistor and its use for the design of a low-phase noise C band sapphire resonator oscillator are also reported. The best measured phase noise (at ambient temperature) is -138 dBc/Hz at 1 kHz offset from a 4.85 GHz carrier frequency, with a loaded Q/sub L/ factor of 75,000.     

An RF-powered, wireless CMOS temperature sensor

We present a wireless, fully integrated CMOS temperature sensor that recovers power from a radio frequency (RF) signal, and returns data as a frequency-modulated 2.3-GHz signal to a base station. Power is recovered from a 450-MHz incident signal with the help of a low-threshold, high-efficiency, voltage rectifier-multiplier circuit. This technique decreases the minimum incident RF power required, compared to state-of-the-art wirelessly powered telemetry systems. The rectifier-multiplier can collect energy from a base station placed up to 18 m away. To further increase the range from the base, the device collects energy in a low power standby/charging mode. A mode selector circuit monitors the amount stored energy and decides if the system is transmitting data or is in the standby/charging mode. A bootstrapped reference generates a complementary to absolute temperature (CTAT) voltage with an R-squared regression of 0.9995 to a linear fit. This reference is used as the temperature sensor of the system, controlling a low-power, integrated, voltage-controlled LC oscillator (VCO). The oscillation frequency of the VCO is modulated by ambient temperature changes. The modulated carrier is transmitted by a fully integrated power amplifier. A temperature sensitivity of 126 ppm//spl deg/C is achieved and the entire sensor consumes 1.1 mA while transmitting data.     

Realization of multiple valued logic and memory by hybrid SETMOS architecture

A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET) hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade oscillations and quasi-periodic negative differential resistance effects at much higher current level than the traditional SETs. The Coulomb blockade oscillation characteristics are exploited to realize the multiple valued (MV) literal gate and the periodic negative differential resistance behavior is utilized to implement capacitor-less multiple valued static random access memory (MV SRAM) cell. The SETMOS literal gate is then used to build up other MV logic building blocks, e.g., transmission gate, binary to MV logic encoder, and MV to binary logic decoder. Analytical SET model simulations are employed to verify the functionalities of the proposed MV logic and memory cells for quaternary logic systems. SETMOS MV architectures are found to be much faster and less temperature-sensitive than previously reported hybrid CMOS-SET based MV circuits.     

Solution-processed ambipolar organic field-effect transistors and inverters

There is ample evidence that organic field-effect transistors have reached a stage where they can be industrialized, analogous to standard metal oxide semiconductor (MOS) transistors. Monocrystalline silicon technology is largely based on complementary MOS (CMOS) structures that use both n-type and p-type transistor channels. This complementary technology has enabled the construction of digital circuits, which operate with a high robustness, low power dissipation and a good noise margin. For the design of efficient organic integrated circuits, there is an urgent need for complementary technology, where both n-type and p-type transistor operation is realized in a single layer, while maintaining the attractiveness of easy solution processing. We demonstrate, by using solution-processed field-effect transistors, that hole transport and electron transport are both generic properties of organic semiconductors. This ambipolar transport is observed in polymers based on interpenetrating networks as well as in narrow bandgap organic semiconductors. We combine the organic ambipolar transistors into functional CMOS-like inverters.     

Accurate and computer efficient modelling of single event transients in CMOS circuits

A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time-consuming and must be performed for each different circuit topology, incident particle and track. The availability of a simple model at the logic gate level may greatly improve circuit sensitivity analysis. The electrical response of a circuit to an ionising particle hit depends on many parameters, such as circuit topology, circuit geometry and waveform shape of the charge injection mechanism. The proposed analytical model, which is accurate and computer efficient, captures these transistor-level effects of ionising particle hits and models them to the logic level of abstraction. The key idea is to exploit a model that allows the rapid determination of the sensitivity of any logic gate in a CMOS circuit, without the need to run circuit simulations. The model predicts whether or not a particle hit generates a SET, which may propagate to the next logic gate or memory element, making possible to analyse the sensitivity of each node in a complex circuit. Model derivation is strongly related to circuit electrical behaviour, being consistent with technology scaling. The model is suitable for integration into CAD tools, intending to make automated evaluation of circuit sensitivity to SET possible, as well as automated estimation of soft error rate     

新型8管一位全加器电路设计

通过对已有全加器电路的研究与分析,提出了仅需8个晶体管的新型全加器单元.新电路包括2个3管同或门模块和1个选择器模块.在台积电(TSMC)0.18μm互补氧化物半导体(CMOS)工艺器件参数下经电路模拟程序(HSPICE)进行性能测试,与现有典型的全加器相比,新电路在晶体管数目、功耗和功耗延迟积有较大的优势.     

Single electron transistor with P-type sidewall spacer gates

A single-electron transistor (SET) is one of the promising solutions to overcome the scaling limit of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). Up to now, various kinds of SETs are being proposed and SETs with a dual gate (DG) structure using an electrical potential barrier have been demonstrated for room temperature operation. To operate DG-SETs, however, extra bias of side gates is necessary. It causes new problems that the electrode for side gates and the extra bias for electrical barrier increase the complexity in circuit design and operation power consumption, respectively. For the reason, a new mechanism using work function (WF) difference is applied to operate a SET at room temperature by three electrodes. Its structure consists of an undoped active region, a control gate, n-doped source/drain electrodes, and metal/silicide or p-type silicon side gates, and a SET with metal/silicide gates or p-type silicon gates forms tunnel barriers induced by work function between an undoped channel and grounded side gates. Via simulation, the effectiveness of the new mechanism is confirmed through various silicide materials that have different WF values. Furthermore, by considering the realistic conditions of the fabrication process, SET with p-type sidewall spacer gates was designed, and its brief fabrication process was introduced. The characteristics of its electrical barrier and the controllability of its control gate were also confirmed via simulation. Finally, a single-hole transistor with n-type sidewall spacer gates was designed.