基于Radix-4实现高速Viterbi译码器设计

使用一种新的Viterbi译码器设计方法来达到高速率、低功耗设计。在传统Viterbi译码器中,ACS(add-compare-select)单元是基于radix-2网格设计的,而这里将介绍一种新的ACS设计方法,即基于radix-4网格的ACS单元设计。每个这样的ACS单元将有4路输入,即在每个时钟周期能够处理两级传统的基于radix-2设计的两级网格。同时在这里的Viterbi译码器设计中采用了Top-To-Down设计思想,用Verilog语言来描述RTL电路层。并用QuartusII软件进行电路仿真和综合。用本算法在33.333MHz时钟下实观在Altera公司的APEX20KFPGA的64状态Viterbi译码器译码速率可达8Mbps以上,且仅占用很小的硬件资源。采用此方法设计的高速Viterbi解码器SoftIPCore可应用于需要高速,低功耗译码的多媒体移动通讯上。     

(2,1,7)维特比译码器结构优化设计与实现

对于维特比译码器设计与实现时速度的制约问题,通过优化加、比、选各单元模块结构,采用模归一化路径度量值和全并行的ACS结构,简化了ACS硬件实现的复杂度并极大地提高了运算速度,为了提高数据吞吐率,幸存路径存储与回溯单元使用4块SRAM优化数据的存储、回溯和译码。利用TSMC0.18逻辑工艺,实现了一种回溯度为64、3bit软判决的(2,1,7)维特比译码器,在1.98V,125℃操作环境下,使用DesignCompiler逻辑综合后静态时序分析,显示数据最大吞吐率为215Mb/s,Astro自动布局布线后的译码器芯片内核面积为1.56mm2,功耗约为103mW。     

Viterbi译码器的硬件实现

介绍了一种Vkerbi译码器的硬件实现方法。设计的基于硬判决的Viterbi译码器具有约束长度长（9)、译码深度深（64)的特点。为了兼顾硬件资源与电路性能两个方面，在设计中使用了4个ACS单元，并根据Xilinx Virtex系列FPGA的结构特点．利用FPGA内部的BlockRAM保存汉明距离和幸存路径，提高了译码速度。     

维特比译码器的路径度量存储更新方法

采用一种新的方法较好地解决了维特比译码器的路径度量存储更新问题,详细介绍了状态地址的映射、加比选(ACS)单元计算顺序的调度、地址产生器的设计,并给出一个64状态8个ACS的维特比译码器的度量存储更新的实例,该方法具有互联面积小、控制逻辑简单和硬件资源消耗少的特点。     

一种低开销双二元turbo译码器设计

设计一种低开销双二元turbo译码器,提出了一种能够适应滑动窗算法的交织器结构,通过与传统方案中的交织器联合使用,大大降低了交织与解交织过程所需要的存储单元.同时将取模归一化(modulo normalization)技术运用到双二元turbo译码器加比选(ACS)模块的设计上,缩短了关键路径的延时,提高了时钟频率和吞吐量.采用FPGA对译码器进行了验证,提出的译码器和传统的译码器相比,存储资源节省12%,和使用存储器存储交织/解交织地址的译码器相比,存储资源节省97%.     

VB高速译码算法及其FPGA实现

根据DVB-T标准中FEC内码的要求,采用FPGA技术实现了R=1/2,64状态,基4,16电平软判决高速Viterbi译码器.通过将原有基2蝶形运算分裂为基4蝶形运算,构造出4路ACS单元.由4个4路ACS单元构成的基4 ACS模块一次可以得到4个状态的两步路径更新,使得译码速度提高了1倍.同时在FPGA设计时进行了减小面积和降低功耗的优化.     

VB高速译码算法及其FPGA实现

根据DVB-T标准中FEC内码的要求,采用FPGA技术实现了R=1/2,64状态,基4,16电平软判决高速Viterbi译码器.通过将原有基2蝶形运算分裂为基4蝶形运算,构造出4路ACS单元.由4个4路ACS单元构成的基4 ACS模块一次可以得到4个状态的两步路径更新,使得译码速度提高了1倍.同时在FPGA设计时进行了减小面积和降低功耗的优化.     

Viterbi Decoder ACS单元中路径度量值存储空间的优化

ACS单元的设计及路径度量(PM)值的存储是Viterbi Decoder硬件实现的重要部分之一。介绍了一种码率为1/2的硬判决Viterbi Decoder的ACS部分的硬件实现方法。采用了一种全新的设计与存储方式,即原位运算旋转地址的方式,极大地节省了在ACS运算过程中用以存储路径度量值的RAM空间,大量的实验证明,设计的译码器在资源消耗上有较大优势。     

适用于IEEE 802.11n的高速低功耗Viterbi译码器的设计

针对IEEE 802.11n SOC对信道编码的多码率、高吞吐率的要求,设计了适用于IEEE 802.11n卷积码的Viterbi译码器,具有高吞吐率,低功耗特点,可支持1/2,2/3,3/4,5/6码率.译码器采用全并行的加比选(ACS)单元,最高位清零防溢出处理,采用了一种可降低功耗的寄存器交换法,可有效减少寄存器翻转动态功耗.采用SMIC0.13tan CMOS工艺设计并实现了该译码器,时钟频率为240MHz时,最大数据吞吐率为480Mb/s,功耗为25mW.     

MB-OFDM UWB系统中高吞吐率Viterbi译码器的实现

提出了一种用于MB-OFDM UWB系统的高吞吐率低功耗Viterbi译码器结构.该结构利用基4蝶形单元的对称性,降低了Viterbi译码器的实现复杂度.采用SMIC 0.131μm CMOS工艺设计并实现了该译码器,在时钟频率为240MHz时,它的最大数据吞吐率为480Mb/s,功耗为135mW.在加性高斯白噪声信道下,它的误码率十分接近理论仿真值.该译码器可用于MB-OFDM UWB系统以及其他高吞吐率低功耗的通信系统中.     

DVB-T中Viterbi译码器的设计及FPGA实现

Viterbi作为一种最大似然译码算法广泛应用在数字地面视频广播中,但由于其较高算法复杂程度,对实现高速低功耗时延小且逻辑结构简单的译码器带来了挑战。首先为了实现高速的Vit-erbi译码器,ACSU采用全并行结构,度量值的溢出控制采用取模归一化方法,并简化比较器。其次为了实现低功耗时延小且控制逻辑简单的Viterbi译码器,SMU采用改进的前向追溯结构,只用一组单口的RAM实现译码输出。该译码器在Xilinx Virtex6上实现并验证通过,并具有较好的译码性能。     

一种双天线发射分集方案的性能分析

在平坦的瑞利衰落信道中,通过分析一种简单的双发射天线分集方案(即Alamouti编码方案,简称ACS)接收信号的统计特性和输出信噪比.在多相相移键控调制下,推导了该方案的传输比特误码率的一般理论分析式,证明了采用ACS技术的移动通信系统与采用2分集阶的最大比率合并接收分集技术的误码性能相同.Monte-Carlo仿真结果也验证此结论.这一理论成果可推广到采用正交空时分组码的多天线发射分集系统.     

Sampling of generalized almost-cyclostationary signals

In this paper, the problem of sampling a continuous-time generalized almost-cyclostationary (GACS) signal is addressed. The class of such nonstationary signals includes, as a special case, the almost-cyclostationary (ACS) signals. ACS signals filtered by some linear time-variant channels are further examples. It is shown that the discrete-time signal constituted by the samples of a GACS signal is a discrete-time ACS signal. Thus, discrete-time ACS signals can arise not only from the sampling of continuous-time ACS signals but from the sampling of a wider class of nonstationary signals as well, namely, the continuous-time GACS signals. In the paper, relationships between generalized cyclic statistics of a continuous-time GACS signal and cyclic statistics of the discrete-time ACS signal constituted by its samples are derived. The problem of aliasing in the domain of the cycle frequencies is considered, and a condition assuring that the cyclic temporal moment function of the discrete-time signal can be obtained by sampling that of the continuous-time signal is determined. Finally, it is shown that, starting from the sampled signal, the GACS or ACS nature of the continuous-time signal can be conjectured, provided that the analysis parameters such as the sampling period, padding factor, and data-record length are properly chosen.     

A quantitative analysis of anonymous communications

This paper quantitatively analyzes anonymous communication systems (ACS) with regard to anonymity properties. Various ACS have been designed & implemented. However, there are few formal & quantitative analyzes on how these systems perform. System developers argue the security goals which their systems can achieve. Such results are vague & not persuasive. This paper uses a probabilistic method to investigate the anonymity behavior of ACS. In particular, this paper studies the probability that the true identity of a sender can be discovered in an ACS, given that some nodes have been compromised. It is through this analysis that design guidelines can be identified for systems aimed at providing communication anonymity. For example, contrary to what one would intuitively expect, these analytic results show that the probability that the true identity of a sender can be discovered might not always decrease as the length of communication path increases.     

EPON系统中ONU应用场景的探讨

以太网无源光网络(EPON)是一种新型的光纤接入技术,它采用点到多点的网络拓扑结构、无源光纤传输。探讨了在实际中根据各种应用场景的不同,系统中的光网络单元(ONU)可以分为单住户单元(SFU)、家庭网关单元(HGU)、单商户单元(SBU)、多住户单元(MDU)和多商户单元(MTU)。指出不同类型的ONU所面向的用户是不同的,所支持的端口类型、端口数目和功能也各不相同。     

High-rate Viterbi processor: a systolic array solution

The main part of the Viterbi algorithm (VA) is a nonlinear feedback loop, the ACS recursion (add-compare-select recursion), which presents a bottleneck for high-speed implementations and cannot be circumvented by standard means. Because the two operations of the loop form an algebraic structure called semiring, it is shown that the ACS recursion of the Viterbi algorithm can therefore be written as a linear vector recursion. This allows the authors to employ the powerful techniques of parallel processing and pipelining, known for conventional linear systems, to achieve high throughput rates. Since the VA can be written as a linear vector recursion, it can be implemented by systolic arrays. For the class of shuffle exchange codes to be decoded by the Viterbi algorithm hardware-efficient code-optimized arrays are presented. It is shown that carry-save arithmetic can be used for the operations of ACS recursion, allowing each word-level operation to be pipelined and carried out by an efficient bit-level systolic array     

非盈利通信建设项目经济评价方法探讨

提出了采用比较类似建设项目和项目建设前后的单位功能投资及单位运营成本的方法来进行非盈利项目的经济可行性评估，评估结果能够作为投资决策的依据。     

基于DriveWindows的穿孔机主传动系统的故障诊断

天津钢管公司168新型钢管厂的穿孔机主传动采用ACS6000SD中压变频传动系统驱动,通过DriveWindows软件对传动系统进行监视、调试和故障诊断,能大大提高效率。本文介绍了DriveWindows的基本功能,重点通过实际故障分析与解决的实例,讲述基于DriveWindows的ACS6000SD中压传动系统的故障诊断。实践表明,使用DriveWindows,能大大提升ACS6000系统的故障分析与解决的效率,使得传动系统能有效安全的运行,具有较大的实用价值。     

A simplified computational kernel for trellis-based decoding

A simplified branch metric and add-compare-select (ACS) unit is presented for use in trellis-based decoding architectures. The simplification is based on a complementary property of best feedforward and some systematic feedback encoders. As a result, one adder is saved in every other ACS unit. Furthermore, only half the branch metrics have to be calculated. It is shown that this simplification becomes especially beneficial for rate 1/2 convolutional codes. Consequently, area and power consumption will be reduced in a hardware implementation.     

An improved pipelined MSB-first add-compare select unit structure for Viterbi decoders

Convolutional codes are widely used in many communication systems due to their excellent error-control performance. High-speed Viterbi decoders for convolutional codes are of great interest for high-data-rate applications. In this paper, an improved most-significant-bit (MSB) -first bit-level pipelined add-compare select (ACS) unit structure is proposed. The ACS unit is the main bottleneck on the decoding speed of a Viterbi decoder. By balancing the settling time of different paths in the ACS unit, the length of the critical path is reduced as close as possible to the iteration bound in the ACS unit. With the proposed retimed structure, it is possible to decrease the critical path of the ACS unit by 12% to 15% compared with the conventional MSB-first structures. This reduction in critical path can reduce the level of parallelism (and area) required for a very high-speed Viterbi decoder.