Adhesion characterization of no-flow underfills used in flip chipassemblies and correlation with reliability

Adhesion is one of the key properties of underfills used in flip chip assemblies. This paper characterizes the adhesion strengths of no-flow underfill materials to various die passivations using the shear test techniques. A novel shear test vehicle with planner underfill layers between the die and substrate is presented. The adhesion strengths and failure modes of the no-flow underfill materials during shear testing correlate well with their thermal shock reliability test results. Underfill adhesion related failures such as delamination and crack are investigated and correlated between flip chip assemblies and shear test vehicle assemblies without solder joint interconnects     

Characterization of underfill materials for functional solderbumped flip chips on board applications

The curing conditions and material properties such as the TCE (thermal coefficient of expansion), T_g (glass transition temperature), flexural storage modulus, tangent delta, and moisture content of nine different underfill materials from three different vendors are measured. Their flow rate and the effect of moisture content on mechanical (shear) strength in solder bumped flip chips on organic substrate are also determined experimentally. Furthermore, their effects on the electrical performance (voltage) of functional flip chip devices on organic substrate are measured. Finally, a simple methodology is presented for the selection of underfills from the measurement results of these nine different underfill materials     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

Mechanical loading of flip chip joints before underfill: the impact on yield and reliability

The underfill-facilitated migration from ceramic to lower cost laminate substrates has become a powerful enabler of direct chip attach by offering lower cost, greater electrical functionality, and a smaller system footprint over comparable packaging technologies. Once underfilled, flip chip on laminate has proven extremely reliable even in severe automotive environments. However, between the process steps of reflow and underfill cure, unprotected flip chip solder joints assembled to laminate boards are susceptible to damage and breakage if mishandled. Here, the survivability and long-term reliability of flip chip joints was studied over a range of applied strains. Mechanical loading of joints was applied via beam deflections of populated, but nonunderfilled, laminate boards. Electrical continuity was monitored before and after testing to determine when the load applied to the flip chip exceeded the joint fracture strength. The propensity for solder joint fracture was then calculated as a function of solder bump size and also as a function of strain rate. Analysis of the mechanical properties of solder revealed assembly strategies which reduce bump damage and eliminate yield loss during the process steps leading up to underfill cure. Both strained and unstrained units were then underfilled and cycled between −50 and +150 °C. While mechanical damage was evident in bump cross-sections of strained flip chip assemblies, the fatigue lives of underfilled solder joints were found to be independent of the size of mechanical loads applied before underfill.     

Field reworkable underfill materials for flip chip on boardassemblies

Studies have shown that underfill encapsulation dramatically improves the solder joint fatigue reliability of flip chip on board (FCOB) assemblies. The lack of reworkability of the underfill after the product is in the field has limited the integration of FCOB into cost sensitive electronic products and the continued proliferation of the FCOB technology will depend on the development of reworkable underfill materials systems. This paper presents data that correlates reliability performance to mechanical properties for twelve field reworkable underfill materials from three different suppliers. Their respective properties, processing parameters, and reliability performances are compared to the qualified, commercially available high performance underfills. Techniques were developed to redress the printed wiring board (PWB) site to enhance the reworked FCOB assembly yield. In addition, reliability performance results and failure analysis observations were compared to the first time nonreworked assemblies     

Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process and no-flow underfill materials

The formation of underfill voids is an area of concern in the low cost, high throughput, or "no-flow" flip chip assembly process. This assembly process involves placement of a flip chip device directly onto the substrate pad site covered with pre-dispensed no-flow underfill. The forced motion of chip placement causes a convex flow front to pass over pad and solder mask-opening features promoting void capture. This paper determines the effects of substrate design on the phenomena of underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing. The substrate design parameters included pad height, solder mask opening height, pad/solder mask opening separation, and pad pitch. The process parameters include chip placement velocity and underfill viscosity. The process robustness is measured in terms of the number of voids created during chip placement, and is further analyzed for the location and any visible modes of void formation. The goal of the work is to determine improved substrate designs to minimize voiding in flip chip processing using no flow underfills.     

Effect of Hygrothermal Aging on Interfacial Reliability of Silicon/Underfill/FR-4 Assembly

The reliability issues have been converted to the underfill adjacent interfaces since the introduction of the underfill to flip chip package in 1990's. Both thermal cycling and hygrothermal conditioning severely attack the interfaces to de- laminate. The moisture migrating into the underfill decreases the adhesion strength, swells to deform the assembly, and weakens the mechanical and thermal properties of the material. In this study, interfacial reliability of a silicon/underfill/FR-4 assembly exposed at 85degC/85%RH was studied using moire interferometry and micro-digital image speckle correlation (mu-DiSC) techniques. A thermal aging study was simultaneously performed to understand the long-term reliability of the assembly. The results showed that the thermal aging relieved the stresses induced by hygrothermal swelling mismatch between dissimilar materials involved, whereas increased the strains induced by hygrothermal swelling. It indicated the time effect is not negligible when the assembly is subjected to the moisture conditioning, otherwise, the deformation induced by the swelling could be overestimated. The mu-DiSC technique was applied to measure the critical interfacial fracture toughness of the silicon/underfill interface. The results showed that the moisture could significantly reduce the interfacial strength due to the break of hydrogen bonding. By combining the moire and mu-DiSC results, it was concluded that the hygrothermal loading could increase the possibility of interfacial delamination in a flip chip package. Finally, the morphologies of the fractured surface were studied with the aid of scanning electron microscope. Remarkable changes of the failure mode were observed.     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

Development of reworkable underfill from hybrid composite of freeradical polymerization system and epoxy resin

The application of the underfill encapsulant is to enhance the solder joint fatigue life in the flip chip assembly, typically up to an order of magnitude, as compared to the nonunderfilled devices. Most of the current underfills, however, are primarily thermosetting epoxy resin curing system based materials, which transform into an infusible three dimensional network structure, and exhibit appreciable adhesion and reliability, but lack of desirable reworkability after curing. From the standpoint of polymeric material chemistry, other thermoplastic or thermosetting polymer materials could be of great economic/cost interest as encapsulants for some microelectronic packaging applications. In this paper, the experimental focus was devoted to the study of adhesion, reliability and reworkability of the free radical polymerization (FRP) system, as well as its hybrid composites or blends with phenoxy resin or epoxy resin (EPR), which could be potential underfill materials. The study encompassed formulation screening based on adhesion measurement, and assessment on reliability and reworkability performance for selected compositions developed so far     

Processing and reliability of CSPs with underfill

The use of chip scale packages (CSPs) is rapidly expanding, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. This paper examines the assembly process with capillary and fluxing underfills. Issues of solder paste versus flux only, solder flux residue cleaning and reworkability are investigated with the capillary flow underfills. Fluxing underfills eliminate the issues of flux-underfill compatibility, but require placement into a predispensed underfill. Voiding during placement is discussed. To evaluate the relative performance of the underfills, a drop test was performed and the results are presented. All of the underfills significantly (5-6x) improved the reliability in the drop test compared to nonunderfilled parts. Test vehicles were also subjected to liquid-to-liquid thermal shock testing. The use of underfill improved the thermal shock performance by /spl ges/5x.     

Yield analysis and process modeling of low cost, high throughputflip chip assembly based on no-flow underfill materials

As a concept to achieve low-cost, high-throughput flip chip on board (FCOB) assembly, a new process has been developed implementing next generation flip chip processing based no-flow fluxing underfill materials. The low-cost, high throughput flip chip process implements large area underfill printing, integrated chip placement and underfill flow and simultaneous solder interconnect reflow and underfill cure. The goals of this study are to demonstrate feasibility of no flow underfill materials and the high throughput flip chip process over a range of flip chip configurations, identify the critical process variables affecting yield, analyze the yield of the high throughput flip chip process, and determine the impact of no-flow underfill materials on key process elements. Reported in this work is the assembly of a series of test vehicles to assess process yield and process defects. The test vehicles are assembled by depositing a controlled mass of underfill material on the chip site, aligning chip to the substrate pads, and placing the chip inducing a compression type underfill flow. The assemblies are reflowed in a commercial reflow furnace in an air atmosphere to simultaneously form the solder interconnects and cure the underfill. A series of designed experiments identify the critical process variables including underfill mass, reflow profile, placement velocity, placement force, and underfill material system. Of particular interest is the fact that the no-flow underfill materials studied exhibit an affinity for unique reflow profiles to minimize process defects     

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials.     

Double bump flip-chip assembly

Capillary underfill remains the dominate process for underfilling Hip-chip die both in packages and for direct chip attach (DCA) on printed circuit board (PCB) assemblies. Capillary underfill requires a post reflow dispense and cure operation, and the underflow time increases with increasing die area and decreasing die-to-substrate spacing. Fluxing or no-How underfills are dispensed prior to die placement and cure during the solder reflow cycle. Since filler particles in the fluxing underfill can be trapped between the solder ball and the substrate pad during placement, the filler content of fluxing underfills is typically limited to <20% or assembly yield drops dramatically. At 20% filler concentration, the coefficient of thermal expansion (CTE) of the underfill is near that of the bulk resin (50-80 ppm//spl deg/C). In this paper, a double bump Hip-chip process is described. A filled capillary underfill is coated onto a wafer and cured. The wafer is then polished to expose the solder bumps. A second solder bump is formed over the original bump by stencil printing solder paste. After dicing, the die is assembled to the PCB using unfilled fluxing underfill. In the resulting structure, the low CTE underfill is near the low CTE Si die, and the higher CTE underfill is in contact with the PCB. In addition, the standoff height is increased compared to a conventional single bump assembly. In air-to-air thermal shock tests, the double bump assembly was /spl sim/ 1.5 X more reliable than the conventional single bump construction with fluxing underfill. Modeling results are also presented.     

Dependence of Flip Chip Solder Reliability on Filler Settling

Thermomechanical reliability of solder joints in flip-chip packages is usually analyzed by assuming a homogeneous underfill ignoring the settling of filler particles. However, filler settling does impact flip chip reliability. This paper reports a numerical study of the influence of filler settling on the fatigue estimation of flip-chip solder joints. In total, nine underfill materials ( 35 vol% silica filler in three epoxies with three filler settling profiles for each epoxy) are individually introduced in a 2-D finite element (FE) model to compare the thermal response of flip chip solder joints that are surrounded by the underfill. The results show that the fatigue indicators for the solder joints (inelastic shear strain increments and inelastic shear strain energy density) corresponding to a gradual, nonuniform filler profile studied in this paper can be smaller than those associated with the uniform filler profile, suggesting that certain gradual filler settling profiles in conjunction with certain resin grades may favor a longer solder fatigue lifetime. The origin of this intriguing observation is in the fact that the solder fatigue indicators are a function of the thermal mismatch among the die, substrate, solder, and underfill materials. The thermal mechanics interplayed among these materials along with a gradual filler profile may allow for minimizing thermal mismatch; and thus lead to lower fatigue indicators.      

Adhesion and toughening mechanisms at underfill interfaces forflip-chip-on-organic-substrate packaging

The flip chip-on-organic-substrate packaging technology utilizes a particulate reinforced epoxy as the underfill (UF) to adhere the chip to the package or board, Although the use of underfill encapsulation leads to improved reliability of flip-chip solder interconnections, delamination at various interfaces becomes a major concern for assembly yield loss and package reliability. In spite of their importance, the adhesion and fracture behaviors of the underfill interfaces have not been investigated until recently. Considerable controversy exists over the effects of underfill formulation and the adhesion and toughening mechanisms of the interfaces. The present work focuses on investigating the effects of several key variables on the interface adhesion strengths for UF/chip and UF/organic substrate systems. These variables are underfill organosilane content, filler particle content, rubber particle content, surface morphology and chemistry of the chip and organic substrates. The approach of this study is to measure the effect of these variables on the interfacial fracture energy using the double-cantilever-beam (DCB) techniques. The results demonstrate that the underfill interfacial adhesion and fracture characteristics are controlled by several distinct but competing mechanisms, such as formation of primary bonds, crack-pinning by glass fillers, debonding of glass filler from epoxy matrix (defect formation), and cavitation and shearing induced by rubber particles. Fundamental understanding of the interfacial adhesion and toughening mechanisms can provide guidance for developing new processes and materials to enhance interfacial adhesion and reliability     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

Surface property of passivation layer on integrated circuit chip and solder mask layer on printed circuit board

Adhesion of underfill to passivation layer on integrated circuit chip and solder mask layer on printed circuit board is critical to the reliability of an underfilled flip chip package. In this study, the surface properties of solder mask and four passivation materials: benzocyclobutene (BCB), polyimide (PI), silicon dioxide (SiO/sub 2/), and silicon nitride (SiN) were investigated. A combination of both wet and dry cleaning processes was very effective to remove contaminants from the surface. The element oxygen, introduced during O/sub 2/ plasma treatment or UV/O/sub 3/ treatment, led to the increase of the base component of surface tension. X-ray photoelectron spectroscopy (XPS) experiments confirmed the increase of oxygen concentration at the surface after UV/O/sub 3/ treatment. Wetting of underfill on passivation and solder mask was slightly improved at higher temperatures. Although UV/O/sub 3/ cleaning and O/sub 2/ plasma treatment significantly improved the wetting of underfill on passivation materials, they did not improve adhesion strength of epoxy underfill to passivation. Therefore, the wetting was not the controlling factor in adhesion of the system studied.     

Assembly of lead-free bumped flip-chip with no-flow underfills

Lead-free solder reflow process has presented challenges to no-flow underfill material and assembly. The currently available no-flow underfill materials are mainly designed for eutectic Sn-Pb solders. This paper presents the assembly of lead-free bumped flip-chip with developed no-flow underfill materials. Epoxy resin/HMPA/metal AcAc/Flux G system is developed as no-flow underfills for Sn/Ag/Cu alloy bumped flip-chips. The solder wetting test is conducted to demonstrate the fluxing capability of the underfills for lead-free solders. A 100% solder joint yield has been achieved using Sn/Ag/Cu bumped flip-chips in a no-flow process. A scanning acoustic microscope is used to observe the underfill voiding. The out-gassing of HMPA at high curing temperatures causes severe voiding inside the package. A differential scanning calorimeter (DSC) used to study the curing degree of the underfill after reflow with or without post-cure. The post-curing profiles indicate that the out-gassing of HMPA would destroy the stoichiometric balance between the epoxy and hardener, and result in a need for high temperature post-cure. The material properties of the underfills are characterized and the influence of underfill out-gassing on the assembly and material properties is investigated. The impact of lead-free reflow on the material design and process conditions of no-flow underfill is discussed.     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法 ,确定了倒装焊 Sn Pb焊点的热循环寿命 .采用粘塑性和粘弹性材料模式描述了 Sn Pb焊料和底充胶的力学行为 ,用有限元方法模拟了 Sn Pb焊点在热循环条件下的应力应变过程 .基于计算的塑性应变范围和实验的热循环寿命 ,确定了倒装焊 Sn Pb焊点热循环失效 Coffin- Manson经验方程的材料参数 .研究表明 ,有底充胶倒装焊 Sn Pb焊点的塑性应变范围比无底充胶时明显减小 ,热循环寿命可提高约 2 0倍 ,充胶后的焊点高度对可靠性的影响变得不明显