Reliability issues for flip-chip packages

In this article, we review the reliability issues for plastic flip-chip packages, which have become an enabling technology for future packaging development. The evolution of area-array interconnects with high I/O counts and power dissipation has made thermal deformation an important reliability concern for flip-chip packages. Significant advances have been made in understanding the thermo-mechanical behavior of flip-chip packages based on recent studies using moiré interferometry. Results from moiré studies are reviewed by focusing on the role of the underfill to show how it reduces the shear strains of the solder balls but shifts the reliability concern to delamination of the underfill interfaces. The development of the high-resolution moiré interferometry based on the phase-shift technique provided a powerful method for quantitative analysis of thermal deformation and strain distribution for high-density flip-chip packages. This method has been applied to study plastic flip-chip packages and the results and impacts on delamination at the die/underfill interface and in the underfill region above the plated through-hole via are discussed. Here a related reliability problem of die cracking during packaging assembly and test is also discussed. Finally, we discuss briefly two emerging reliability issues for advanced flip-chip packages, one on the packaging effect on Cu/low k interconnect reliability and the other on electromigration of solder balls in flip-chip packages.     

Reliability issues of low-cost overmolded flip-chip packages

A significant need exists for the determination of critical stress characteristics within the low-cost overmolded flip-chip (OM-FC) packages. A systematic stress analysis is reported to investigate the OM-FC package for the optimal design of package geometries, materials combinations during the attachment, and thermal testing processes. A parametric study is conducted seeking the best package performance during the identified most stringent process which causes the largest stress within the low-cost substrate. High-stress location is predicted by finite-element analysis, and it was found that mold compound (MC) curing is the most stringent process for the reliability of substrate; higher underfill fillet, thicker die, larger die size without causing edge effect, solder mask defined structure resulted in smaller stresses in substrate. MC with lower coefficient of thermal expansion is a preferable and compliant substance that is good for using as molding and underfill material     

Inductance-controlled electroabsorption Modulator modules using the flip-chip bonding technique

The wire-bonding technique is widely used for the connections between the electroabsorption (EA) modulator chips and the electrical signal transmission lines. However, the parasitic inductance of the bonding wire degrades the electrical characteristics of the EA modulator modules in a high-frequency region. In this paper, we theoretically analyze the influence of parasitic inductance on the base-band digital transmission and obtain the relationship between the EA modulator capacitance and the optimum lead inductance. For precise inductance control, we introduced the flip-chip bonding (FCB) technique and fabricated 40-Gb/s EA modulator modules.     

Effect of nonconducting filler additions on ACA properties and thereliability of ACA flip-chip on organic substrates

We investigated the effect of nonconducting fillers on the thermomechanical properties of modified anisotropic conductive adhesive (ACA) composite materials and the reliability of flip chip assembly on organic substrates using modified ACA composite materials. For the characterization of modified ACAs composites with different content of nonconducting fillers, dynamic scanning calorimetry (DSC), thermogravimetric analysis (TGA), dynamic mechanical analysis (DMA), and thermomechanical analysis (TMA) were utilized. As the nonconducting filler content increased, CTE values decreased and storage modulus at room temperature increased. In addition, the increase in the content of filler brought about the increase of T_g(DSC) and T_g(TMA). However, the TGA behaviors stayed almost the same. Contact resistance changes were measured during reliability tests such as thermal cycling, high humidity and temperature, and high temperature at dry condition. The reliability results were significantly influenced by CTEs of ACA materials, especially at the thermal cycling tests. Results showed that flip chip assembly using modified ACA composites with lower coefficients of thermal expansion (CTEs) and higher modulus by loading nonconducting fillers exhibited better contact resistance behavior than conventional ACAs without nonconducting fillers     

Patterning of organic photovoltaic modules by ultrafast laser

In this paper, we demonstrate that laser patterning of organic solar cells by ultrafast laser systems (pulse length <350 fs) is an attractive process to produce photovoltaic modules with outstanding high geometric fill factors. Moreover, in terms of precision, registration, and debris generation and in terms of keeping the damage to the underneath layers at a minimum, ultrafast laser patterning with a pulse length of few hundreds of femtoseconds turns out to yield superior results. Ablation of all three different solar cell layers (electrodes (P1 and P3) and interfaces and semiconductor (P2)) is achieved with a single wavelength simply by a precise adjustment of the laser fluence and the patterning overlap. Camera positioning allows a precise registration between the various processing steps and a reduction of the width of the overall interconnection regime to the hundreds of micrometers dimension, resulting in high geometrical fill factors of over 90% for monolithically interconnected organic solar cell modules. Copyright © 2013 John Wiley & Sons, Ltd.     

Design issues of a three-dimensional packaging scheme for power modules

This paper presents design issues of a novel three-dimensional packaging approach for power modules. Solder interconnections are implemented on power devices (insulated gate bipolar transistors and diodes) to obtain vertical interconnections for the proposed multi-layer packaging technique. Issues related to materials selection and processing, electrical and thermo-mechanical aspects of implementing the new packaging concept are discussed.     

Power cycling issues and challenges of SiC-MOSFET power modules in high temperature conditions

Silicon carbide (SiC) MOSFETs power modules are very attractive devices and are already available in the market. Nevertheless, despite technological progress, reliability remains an issue and reliability tests must be conducted to introduce more widely these devices into power systems. Because of trapping/de-trapping phenomena at the SiC/SiO₂ interface that lead to the shift of threshold voltage, test protocols based on silicon components cannot be used as is, especially in high temperature conditions. Using high temperature SiC MOSFET power modules, we highlight the main experimental difficulties to perform power cycling tests. These reversible physical mechanisms preclude the use of temperature sensitive parameters (TSEP) for junction temperature measurements, so we set up fiber optic temperature sensors for this purpose. Moreover, these degradation phenomena lead to difficulties in both controlling the test conditions and seeking for reliable aging indicator parameters. Finally, a power cycling test protocol at high temperature conditions is proposed for such devices.     

Void-effect modeling of flip-chip encapsulation on ceramicsubstrate

A detailed numerical and experimental study of the thermal-mechanical stress and strain in the solder bumps (C4s) of a flip-chip ceramic chip carrier has been completed. The numerical model used was based upon the finite element method. The model simulated accelerated thermal cycling (ATC) from 0°C to 100°C. Several parametric studies were conducted, including the effects of chip size, micro-encapsulation, and the effect of the presence of voids in the micro-encapsulant. It was notably found that the presence of voids in the encapsulant does not significantly increase the stress/strain in the C4s, with the exception of very large voids and voids at or near the edge of the chip     

Electromigration-induced failure in flip-chip solder joints

The electromigration failure mechanism in flip-chip solder joints through the rapid dissolution of the Cu metallization was studied in detail. The ambient temperature was found to be a very important factor in this failure mechanism. When the ambient temperature was changed from 100°C to 70°C, the time to failure changed from 95 min to 31 days. The results of this study indicate that temperature, as an experimental variable, is not less important than the current density in electromigration study. The surface temperatures of the chip and substrate during electromigration were also measured. The temperature of the Si chip was reasonably homogeneous because of the fact that Si is a very good thermal conductor. It was also reasoned that the high thermal conductivity of the PbSn solder could not support a temperature gradient large enough to induce thermomigration across the solder joint in the present study. Experimentally, no evidence of mass transport caused by thermomigration was observed.     

Surface treatment patterning of organic photovoltaic films for low-cost modules

This work describes a patterning technique for the photoactive layer of organic photovoltaic modules. We demonstrate the fabrication of efficient poly[3-(hexyl)thiophene-2,5-diyl]:[6,6]-phenyl-C61-butyric acid methyl ester (P3HT:PCBM) based organic photovoltaic modules through a specific surface treatment, based on the deposition of a fluorinated self assembled monolayer (SAM) on top of the bottom electric contact. Direct self-patterning of the photoactive layer is achieved by the high contact angle between the SAM and the polymer solution, while a smooth topography is created by combining two solvents with different surface tensions and boiling points in the polymer:PCBM solution. The resolution of the patterning is approximately 400 μm for modules based on a conventional cell architecture and 120 μm for an inverted architecture. As a result, we show 25 cm² P3HT:PCBM based organic photovoltaic modules with 10 series-connected cells, fabricated via roll-to-roll compatible deposition and patterning techniques.     

High-power flip-chip blue light-emitting diodes based on AlGaInN

The design and fabrication of a high-power light-emitting diode chip that has an active-region area of 1 mm² and emits at a wavelength of 460 nm are described. The chip structure is developed on the basis of numerical simulation and is intended for flip-chip assembly. The use of two-level interconnections for an n-type contact made it possible to obtain an unprecedentedly low series resistance (0.65 Ω) and a high uniformity of pump-current distribution. Light-emitting diodes based on the developed design operate in the continuous-wave mode in a current range of 0–2 A, and their highest emission power is 430 mW.     

Three-dimensional flip-chip on flex packaging for power electronicsapplications

We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM     

Effect of polyimide baking on bump resistance in flip-chip solder joints

The effect of polyimide (PI) thermal process on the bump resistance of flip-chip solder joint is investigated for 28 nm technology device with aggressive extreme low-k (ELK) dielectric film scheme and lead-free solder. Kelvin structure is designed in the bump array to measure the resistance of single solder bump. An additional low-temperature pre-baking before standard PI curing increases the bump resistance from 9.3 mΩ to 225 mΩ. The bump resistance increment is well explained by a PI outgassing model established based on the results of Gas Chromatography–Mass Spectrophotometer (GC–MS) analysis. The PI outgassing substances re-deposit on the Al bump pad, increasing the resistance of interface between under-bump metallurgy (UBM) and underneath Al pad. The resistance of interface is twenty-times higher than pure solder bump, which dominates the measured value of bump resistance. Low-temperature plasma etching prior to UBM deposition is proposed to retard the PI outgassing, and it effectively reduces the bump resistance from 225 mΩ to 10.8 mΩ.     

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.     

Emission distribution in GaInAsSb/GaSb flip-chip diodes

Results obtained in studies of the near-field pattern of GaInAsSb IR flip-chip light-emitting diodes (LEDs) operating in the 2 μm range are presented. The electrical and reflective properties of ohmic contacts are discussed and the near-field emission distribution is analyzed in relation to the current and electrical and geometrical parameters of the LEDs.

     

Characteristics of current crowding in flip-chip solder bumps

For a flip-chip package assembly, current crowding occurs in the vicinity of the locations where traces connect the solder bumps. This feature contributes significantly to the electromigration failure of the solder bumps. In this study the finite element analysis is performed to investigate characteristics of current crowding in a flip-chip solder bump subjected to a constant applied current. It is found that under such a condition, current crowding is induced solely by the structural geometry of the system. It is independent of the magnitude of the applied current. A volumetric averaging technique is also applied to cope with the current crowding singularity.     

Flow time measurements for underfills in flip-chip packaging

Flow time is a key material property for underfill materials in flip-chip applications. In this paper, we will discuss how to use flow time testing for underfill flow evaluation and material screening. The flow time of several underfills was measured at elevated temperatures using test pieces made from glass microscope slides. The material properties impacting underfill flow, such as viscosity, contact angle, and surface tension, were also experimentally measured and used to calculate estimated flow times using the Washburn equation. Empirical and calculated flow times were compared. The effects of channel width and flow distance on flow time were also studied. Additionally, the effect of a tilted stage on flow time, epoxy tongue, and void formation was evaluated.     

Influence of crystallographic orientation of Sn-Ag-Cu on electromigration in flip-chip joint

The influence of the crystallographic orientation of Sn-3.0 wt%Ag-0.5 wt%Cu flip-chip joints and underfill on electromigration was investigated. The current density applied in our tests was 15 kA/cm² at 160 °C. Various times to failure of the test samples show a clear dependence of the electromigration behavior on the Sn grain orientations. Different microstructural evolutions were observed in all solder bumps in correlation with the crystallographic orientations of the Sn grains after an electromigration test. The primary failure of the solder joints was caused by dissolution of the Cu electrode at the cathode interface. Rapid dissolution of the Cu electrode occurred when the c-axis of the Sn grains was parallel to the direction of electron flow. On the other hand, slight dissolution of the Cu electrode was observed when the c-axis of the Sn grains was perpendicular to the direction of electron flow. Some grain boundaries interrupt the migration of Cu and the trapped Cu atoms form new grains of intermetallic compounds at the grain boundaries. In addition, underfill inhibits serious deformation of solder bumps during current stressing.     

Processing and doping of thick polymer active layers for flexible organic thermoelectric modules

While the majority of research on organic thermoelectric generators has focused on individual devices with organic films having thicknesses of several hundred nanometers (nano-films), films with micrometer-scale thicknesses (micro-films) provide a longer thermal conduction path that results in a larger temperature gradient and higher thermoelectric voltages in modules. In this study, the properties of solution-processed nano- and micro-films of the p-type semiconductor P3HT doped with two different dopants, F₄-TCNQ and Fe³⁺-tos₃·6H₂O, were investigated. While doping with F₄-TCNQ resulted in high electrical conductivity only in nano-films, doping with Fe³⁺-tos₃·6H₂O from a 25 mM solution yielded power factors of up to ∼30 μWm⁻¹ K⁻² with a conductivity of 55.4 Scm⁻¹ in micro-films. Changes in the molecular packing were compared based on X-ray diffraction, and the best operational stability in air was found for the Fe³⁺-tos₃·6H₂O-doped micro-films. Using Fe³⁺-tos₃·6H₂O as dopant, flexible thermoelectric modules with solution-processed micro-films patterned by a photo-etching technique that does not require alignment and assembly of individual devices were demonstrated, exhibiting a maximum power output of 1.94 nWK⁻² for a uni-leg module with 48 elements. Analysis of the flexible module performance showed that the performance is limited by the contact resistance, which must be taken into consideration when optimizing module structure.