MESFET fabrication on MOCVD grown Hg/sub 1-x/Cd/sub x/Te

The fabrication of the first MESFET structures on Hg/sub 1-x/Cd/sub x/Te is reported using MOCVD grown layers on GaAs substrates. The 6 mu m gate devices exhibited a room temperature transconductance of 1.0 mS/mm and pinch off voltage of -4.0 V. The Schottky barrier characteristics of the devices were critically dependent on the stoichiometric x ratio of the Hg/sub 1-x/Cd/sub x/Te with diode formation evident only at x >0.5.<>     

1-2 micron (Hg, Cd)Te photodetectors

The performance of mercury cadmium telluride detectors in the 1-2 micron spectral region has been predicted from basic material parameters. Photovoltaic devices should be characterized by specific responsivities of 1 A/W for a 1000 ohm load when transit time limited to less than 20 ns. Photoconductive detectors made from n-type material should have radiative lifetimes of 1 ms. The feasibility of high performance 1-2 micron (Hg, Cd)Te detectors has been demonstrated experimentally. Deep junction devices operating at room temperature without bias have been fabricated by impurity indiffusion. Detectivities at 1.75 microns approached 10¹⁰cm.Hz^1/2/W with open-circuit responsivities of approximately 500 V/W. In addition, 1.5 micron detectors have been fabricated from p-type, 25 Ω.cm material. With no bias at room temperature, these detectors showed D* λ>10¹⁰cm.Hz/12/W, open-circuit responsivities in excess of 10³V/W, and response times on the order of microseconds. These preliminary results indicate that detectors fabricated from the pseudobinary alloy of (Hg, Cd)Te are well suited for high speed, near infrared photodetection in which room temperature operation is required.     

Effects of growth conditions on the composition of CVT and PVT grown Hg1-x Cd x Te epitaxial layers

Single crystal epitaxial layers of Hg_1-x Cd _x Te were grown on CdTe substrates employing the chemical and physical vapor transport techniques. Different growth temperatures and various pressures of HgI₂ as a transport agent were used while the source materials had compositions of eitherx = 0.4 orx = 0.6. The epilayers are of nearly uniform composition to a depth of about one-half of the layer thickness. The Hgl₂ pressure and the growth temperature used for the growth experiments have significant effects on the layer composition. The desired epilayer composition ofx = 0.2 can be achieved with either source compositions by properly adjusting the HgI₂ pressure and the growth temperature.     

Investigations of high-performance GaAs solar cells grown on Ge-Si/sub 1-x/Ge/sub x/-Si substrates

High-performance p/sup +//n GaAs solar cells were grown and processed on compositionally graded Ge-Si/sub 1-x/Ge/sub x/-Si (SiGe) substrates. Total area efficiencies of 18.1% under the AM1.5-G spectrum were measured for 0.0444 cm/sup 2/ solar cells. This high efficiency is attributed to the very high open-circuit voltages (980 mV (AM0) and 973 mV (AM1.5-G)) that were achieved by the reduction in threading dislocation density enabled by the SiGe buffers, and thus reduced carrier recombination losses. This is the highest independently confirmed efficiency and open-circuit voltage for a GaAs solar cell grown on a Si-based substrate to date. Larger area solar cells were also studied in order to examine the impact of device area on GaAs-on-SiGe solar cell performance; we found that an increase in device area from 0.36 to 4.0 cm/sup 2/ did not degrade the measured performance characteristics for cells processed on identical substrates. Moreover, the device performance uniformity for large area heteroepitaxial cells is consistent with that of homoepitaxial cells; thus, device growth and processing on SiGe substrates did not introduce added performance variations. These results demonstrate that using SiGe interlayers to produce "virtual" Ge substrates may provide a robust method for scaleable integration of high performance III-V photovoltaics devices with large area Si wafers.     

1/f Noise in (Hg, Cd)Te photodiodes

In this article we present results of experiments to characterize 1/fnoise in Hg0.7Cd0.3Te n⁺-on-p junction photodiodes. Under zero-bias voltage conditions, the photodiodes display no 1/fnoise, even in the presence of large photocurrents. Under reverse-bias voltage operation, 1/fnoise is observed. In these experiments, the 1/fnoise was measured as a function of temperature, diode bias voltage, and photon flux. Since these parameters varied the relative contributions of the various current mechanisms, the diode current mechanism responsible for 1/fnoise was isolated. It was found that 1/fnoise is independent of photocurrent and diffusion current but is linearly related to surface generation current. It is proposed that 1/fnoise in reverse-biased (Hg, Cd)Te photodiodes is a result of modulation of the surface generation current by fluctuations in the surface potential.     

High frequency performance of Si/sub 1-x/Ge/sub x//Si/sub 1-y/Ge/sub y//Si/sub 1-x/Ge/sub x/ HBTs

The results of a theoretical study of the performance of high speed SiGe HBTs is presented. The study includes a group of SiGe HBTs in which the Ge concentration in the base is 20% higher than that in the emitter and collector (i.e. y=x+0.2). It is shown that the composition dependences of f/sub T/ and the F/sub max/ are non-monotonic. As the Ge composition in the emitter and collector layers is increased, f/sub T/ and f/sub max/ first decrease, then remain constant and finally increase to attain their highest values.<>     

The origin of hillocks in (Hg, Cd)Te grown by MOVPE

Dimethylcadmium, a precursor for the metalorganic vapor phase epitaxy of mercury cadmium telluride, has been shown to react with gallium arsenide to form trimethylarsine and dimethylarsine. An analogous reaction occurs between di-iso-propyltelluride and gallium arsenide to form iso-propylarsine and di-iso-propylarsine. It is proposed that if these reactions remove sufficient arsenic from a gallium arsenide substrate, metallic droplets will form on the wafer surface thereby creating the nucleation sites for hillocks. Analogous reactions have been observed between the precursors and a range of other substrates which can in turn be used to explain the origin of hillocks in epitaxial layers grown onto these materials.     

GaAs/Al/sub x/Ga/sub 1-x/As quantum well infra-red photodetectors with cutoff wavelength lambda /sub c/=14.9 mu m

The longest wavelength quantum well infra-red photo-detector (QWIP) ever measured with a cutoff wavelength of lambda /sub c/=14.9 mu m is demonstrated when cooled to 10 K. Prospects for even longer wavelength detectors are promising.<>     

High-performance, metamorphic In/sub x/Ga/sub 1-x/As tunnel diodes grown by molecular beam epitaxy

Thin In/sub x/Ga/sub 1-x/As tunnel junction diodes having compositions from x=0.53 to 0.75 that span a range of bandgap energies from 0.74 to 0.55 eV, were grown on InP and metamorphic, step-graded In/sub x/Al/sub 1-x/As/InP substrates using molecular beam epitaxy and evaluated in the context of thermophotovoltaic (TPV) applications. Both carbon and beryllium were investigated as acceptor dopants. Metamorphic tunnel diodes with a bandgap of 0.60 eV (x=0.69) using carbon acceptor doping displayed highest peak current densities, in excess of 5900 A/cm/sup 2/ at a peak voltage of 0.31 V, within a 200 /spl Aring/ total thickness tunnel junction. Identically doped lattice-matched tunnel diodes with a bandgap of 0.74 eV exhibited lower peak current densities of approximately 2200 A/cm/sup 2/ at a higher peak voltage of 0.36 V, consistent with the theoretical bandgap dependence expected for ideal tunnel diodes. Specific resistivities of the 0.60 eV bandgap devices were in the mid-10/sup -5/ /spl Omega/-cm/sup 2/ range. Together with their 200 /spl Aring/ total thickness, the electrical results make these tunnel junctions promising for TPV applications where low-resistance, thin metamorphic tunnel junctions are desired.     

Low-temperature annealing of (Hg,Cd)Te

Many methods for the employment of (Hg,Cd)Te alloys employ anneals at temperatures <300°C to convert the p type left over from the growth process or to adjust the concentration of the native acceptors. An investigation of the kinetics of this annealing process has been performed as functions of (1) vacancy concentration; (2) composition, or the CdTe mole fraction in the alloy; and (3) temperature. If these anneals are carried out under mercury-saturated conditions, the tellurium precipitates in the material, which result either from the growth process or from specific thermal histories, are annihilated by in-diffusing mercury, which results in a significant multiplication of dislocations. This interface, delineated by defect etching, has been employed to investigate the kinetics of the annealing process. These results will be unaffected by the uncertainties introduced in determining this interface by electrical measurements, which arise from incomplete ionizations of the metal vacancies at 77 K for Hg_1−xCd_xTe with CdTe mole fractions exceeding ∼0.26. The annealing rate appears to be strongly dependent on both the temperature and composition of the alloy, decreasing with increasing CdTe mole fraction, within 0.15 and 0.5, with the behavior resembling a composition-dependent, activated-diffusion process. The depth of the interface appears to vary inversely as the root of the metal-vacancy concentration.     

Noise performance of Si/Si/sub 1-x/Ge/sub x/ FETs

Noise characteristics are evaluated for SiGe/Si based n-channel MODFETs and p-channel MOSFETs. The analysis is based on a self-consistent solution of Schrodinger and Poisson's equations. The model predicts a superior minimum noise figure for an n-channel MODFET at 77 K. P-channel MOSFETs behave similar to n-channel devices operating at 300 K. Minimum noise figure decreases with increasing quantum well (QW) width for both n- and p-channel devices. However, the p-channel devices are less sensitive to QW width variation. Minimum noise temperature behaves similarly. As observed, a range of doped epilayer thickness exists where minimum noise figure is a minimum for both n- and p-channel FETs.<>     

Al/sub 0.3/Ga/sub 0.7/As/In/sub x/Ga/sub 1-x/As (0/spl les/x/spl les/0.25) doped-channel field-effect transistors (DCFET's)

The properties of both lattice-matched and strained doped-channel field-effect transistors (DCFET's) have been investigated in AlGaAs/In/sub x/Ga/sub 1-x/As (0/spl les/x/spl les/0.25) heterostructures with various indium mole fractions. Through electrical characterization of grown layers in conjunction with the dc and microwave device characteristics, we observed that the introduction of a 150-/spl Aring/ thick strained In/sub 0.15/Ga/sub 0.85/As channel can enhance device performance, compared to the lattice-matched one. However, a degradation of device performance was observed for larger indium mole fractions, up to x=0.25, which is associated with strain relaxation in this highly strained channel. DCFET's also preserved a more reliable performance after biased-stress testings.<>     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

On the threshold Voltage of strained-Si-Si/sub 1-x/Ge/sub x/ MOSFETs

The threshold voltage shifts (/spl Delta/V/sub t(SS)/ relative to V/sub t/ of Si-control devices) in strained-Si-Si/sub 1-x/Ge/sub x/ (SS) CMOS devices are carefully examined in terms of the shifted two-dimensional energy subbands and the modified effective conduction- and valance-band densities of states. Increased electron affinity as well as bandgap narrowing in the SS layer are shown to be the predominant components of /spl Delta/V/sub t(SS)/, whereas the density-of-state terms tend to be relatively small but not insignificant. The study reveals, for both n-channel and p-channel SS MOSFETs, important physical insights on the varied surface potential at threshold, defined by energy quantization as well as the strain, and on the shifted flat-band voltage that is also part of /spl Delta/V/sub t(SS)/. Models for /spl Delta/V/sub t(SS)/ dependent on the Ge content (x), with comparisons to published data, are presented and used to show that redesign of channel doping in the SS nMOSFET to increase the significantly reduced V/sub tn(SS)/ for off-state current control tends to substantively diminish the inherent SS CMOS relative speed enhancement, e.g., by more than 40% for x=0.20. Interestingly, the SS pMOSFET model predicts small increases in the magnitude of V/sub tp(SS)/.     

Ultralow leakage In/sub 0.53/Ga/sub 0.47/As p-i-n photodetector grown on linearly graded metamorphic In/sub x/Ga/sub 1-x/P buffered GaAs substrate

A novel top-illuminated In/sub 0.53/Ga/sub 0.47/As p-i-n photodiodes (MM-PINPD) grown on GaAs substrate by using linearly graded metamorphic In/sub x/Ga/sub 1-x/P (x graded from 0.49 to 1) buffer layer is reported. The dark current, optical responsivities, noise equivalent power, and operational bandwidth of the MM-PINPD with aperture diameter of 60 /spl mu/m are 13 pA, 0.6 A/W, 3.4/spl times/10/sup -15/ W/Hz/sup 1/2/, and 7.5 GHz, respectively, at 1550 nm. The performances of the MM-PINPD on GaAs are demonstrated to be comparable to those of a similar device made on InGaAs-InP substrate.     

Characteristics of In/sub x/Al/sub 1-x/N-GaN high-electron mobility field-effect transistor

GaN-based field effect transistors commonly include an Al/sub x/Ga/sub 1-x/N barrier layer for confinement of a two-dimensional electron gas (2DEG) in the barrier/GaN interface. Some of the limitations of the Al/sub x/Ga/sub 1-x/N-GaN heterostructure can be, in principle, avoided by the use of In/sub x/Al/sub 1-x/N as an alternative barrier, which adds flexibility to the engineering of the polarization-induced charges by using tensile or compressive strain through varying the value of x. Here, the implementation and electrical characterization of an In/sub x/Al/sub 1-x/-GaN high electron mobility transistor with Indium content ranging from x=0.04 to x=0.15 is described. The measured 2DEG carrier concentration in the In/sub 0.04/Al/sub 0.96/N-GaN heterostructure reach 4/spl times/10/sup 13/ cm/sup -2/ at room temperature, and Hall mobility is 480 and 750 cm/sup 2//V /spl middot/ s at 300 and 10 K, respectively. The increase of Indium content in the barrier results in a shift of the transistor threshold voltage and of the peak transconductance toward positive gate values, as well as a decrease in the drain current. This is consistent with the reduction in polarization difference between GaN and In/sub x/Al/sub 1-x/N. Devices with a gate length of 0.7 /spl mu/m exhibit f/sub t/ and f/sub max/ values of 13 and 11 GHz, respectively.     

Properties of Si/sub 3/N/sub 4//Si/sub x/Ge/sub 1-x/ metal-insulator-semiconductor capacitors

The density of fast interface states was studied in Si/sub 3/N/sub 4//Si/sub 0.8/Ge/sub 0.2/ metal-insulator-semiconductor (MIS) capacitors. The interface state density does not appear to be strongly affected by the presence of a thin Si interlayer between the nitride and SiGe alloy. This is in contrast to the results when SiO/sub 2/ is used as the insulator material in similar structures.<>     

Avalanche noise characteristics of single Al/sub x/Ga/sub 1-x/As(0.3

Groves  C. Chia  C.K. Tozer  R.C. David  J.P.R. Rees  G.J. 《Quantum Electronics, IEEE Journal of》2005,41(1):70-75