SiC-MOS界面优化的工艺验证及MOSFET电学特性仿真拟合

SiC因其优越的电学特性,已发展成为高压功率器件领域的翘楚。然而,SiC与SiO₂界面存在高密度界面态,使得SiC MOSFET沟道迁移率远低于SiC材料本身的体迁移率,大大约束了SiC材料本身电学性能的发挥。为改善反型层沟道迁移率,不同功率器件厂商采用了不同的栅极氧化工艺,所实现的栅极氧化层界面态密度各有不同,现有的功率器件仿真软件提供的多种界面态能级分布模型都需要芯片厂商实际的流片数据作为支撑,这对功率器件上游设计人员产生了阻碍。基于此,文章通过流片测试数据,结合TCAD仿真软件给出了一种用于SiC MOSFET器件仿真的界面态能级分布模型。利用给出的界面态能级分布模型,与实际产品对比,仿真得出的I-V曲线与测试曲线基本重合。     

SiO_2/SiC界面陷阱对SiC MOSFET开关损耗的影响

位于SiO_2/SiC界面处密度较高的陷阱,不仅俘获SiC MOSFET沟道中的载流子,而且对沟道中的载流子形成散射、降低载流子的迁移率,因而严重影响了SiC MOSFET的开关特性。目前商业化的半导体器件仿真软件中迁移率模型是基于Si器件开发,不能体现SiO_2/SiC界面处的陷阱对沟道中载流子的散射作用。通过引入能正确反映界面陷阱对载流子作用的迁移率模型,利用半导体器件仿真软件研究了界面陷阱对SiC MOSFET动态特性的影响。结果表明,随着界面陷阱密度的增加,SiC MOSFET开通过程变慢,开通损耗增加,而关断过程加快,关断损耗减小;但是由于沟道载流子数量的减少、导通电阻的增加,总损耗是随着界面陷阱密度的增加而增加。     

6H-SiC埋沟MOSFET的C-V解析模型研究

研究了6H-SiC埋沟MOSFET器件的电容-电压特性,建立了解析模型.具体分析了埋沟MOSFET各种工作模式下的电容与栅电压之间的关系,考虑了SiO2/SiC界面态及pn结对电容-电压特性的影响.对模型进行了仿真分析验证,结果表明:在假设界面态密度分布均匀条件下,由于对界面态做了简化处理,因而在耗尽模式及夹断模式下的C-V特性计算结果与实验结果有所差异.     

耗尽型4H-SiC埋沟MOSFET器件解析模型研究

建立了基于漂移扩散理论的4H-SiC埋沟MOSFET器件的物理解析模型。SiC/SiO_2界面处的界面态密度及各种散射机制都会导致器件载流子迁移率的下降,采用平均迁移率模型,分析散射机制对载流子迁移率的影响,讨论了界面态对阈值电压的影响。考虑到器件处在不同工作模式下,沟道电容会随栅压的变化而改变,采用了平均电容概念。器件仿真结果表明:界面态的存在导致漏极电流减小;采用平均迁移率模型得到的计算结果与实验测试结果较为一致。     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

一氧化氮退火对高温氧化SiC/SiO2界面特性的影响研究

本文研究了高温（1300℃）氧化并在一氧化氮（NO）气体中进行氧化后退火方法对4H-SiC 金属-氧化物-半导体（MOS）电容的SiC/SiO2界面特性的影响,主要通过SiC MOS的电容-电压(C-V)特性详细讨论了NO退火时间和温度与SiO2/SiC界面特性的相互关系. 结果表明在NO气体中进行氧化后退火可明显降低界面态密度,并且界面态密度随着温度和时间的增加会进一步降低。 同时,与常规1200℃及以下氧化温度相比,1300℃下热生长的氧化层具有更低的界面态密度且显著缩短了氧化时间,节约了生产成本。     

氧化后退火技术对SiO2/4H-SiC界面态密度的影响

采用等离子体增强化学气相沉积(PECVD)低温处理和高温快速退火的技术,研究了退火条件对SiO2/4H-SiC界面态密度的影响.在n型4H-SiC外延片上高温干氧氧化50 nm厚的SiO2层并经N2原位退火,随后在PECVD炉中对样品进行350℃退火气氛为PH3,N2O,H2和N2的后退火处理,之后进行高温快速退火,最后制备Al电极4H-SiC MOS电容.I-V和C-V测试结果表明,各样品的氧化层击穿场强均大于9 MV/cm,PH3处理可以降低界面有效负电荷和近界面氧化层陷阱电荷,但PH3处理样品的界面态密度比N2O处理的结果要高.经N2O氛围PECVD后退火样品在距离导带0.2和0.4 eV处的界面态密度分别约为1.7× 1012和4×1011eV-1·cm-2,有望用于SiC MOSFET器件的栅氧处理.     

SiC MOS界面氮等离子体改性及电学特性评价

降低SiO2/SiC界面态密度是SiCMOS器件研究中的关键技术问题。采用氮等离子体处理SiO2/SiC界面,制作MOS电容后通过I-V、C-V测试进行氧化膜可靠性及界面特性评价,获得的氧化膜击穿场强约为9.96MV/cm,SiO2/SiC势垒高度2.70eV,同时在费米能级附近SiO2/SiC的界面态密度低减至2.27×1012cm-2eV。实验结果表明,氮等离子体处理SiO2/SiC界面后能有效降低界面态密度,改善MOS界面特性。     

碳化硅MOSFET电学参数的电容-电阻法评估

阈值电压、栅内阻、栅电容是碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)的重要电学参数,但受限于器件寄生电阻、栅介质界面态等因素,其提取过程较为复杂且容易衍生不准确性。文章通过器件建模和实验测试,揭示了MOSFET的栅电容非线性特征,构建了电容-电阻串联电路测试方法,研究了SiC MOSFET的栅内阻和阈值电压特性。分别获得栅极阻抗和栅源电压、栅极电容和栅源电压的变化规律,得到栅压为-10V时的栅内阻与目标值误差小于0.5Ω,以及串联电容相对栅源电压变化最大时的电压近似为器件阈值电压。相关结果与固定电流法作比较,并分别在SiC平面栅和沟槽栅MOSFET中得到验证。因此,该种电容-电阻法为SiC MOSFET器件所面临的阈值电压漂移、栅极开关振荡现象提供较为便捷的评估和预测手段。     

基于磷钝化栅介质的1.2kV 4H-SiC DMOSFET

本文对比了NO退火和磷掺杂两种栅钝化工艺,其中磷钝化采用了平面扩散源进行掺杂,通过C-V特性进行了4H-SiC/SiO₂界面特性评价,使用Terman法分析计算获得距导带底0.2-0.4eV范围内界面态密度.结果表明引入磷比氮能更有效降低界面态密度,提高沟道载流子迁移率.其次,对比了两种栅钝化工艺制备的4H-SiC DMOSFET器件性能,实验表明采用磷钝化工艺处理的器件性能更优.最后,基于磷掺杂钝化工艺首次制备出击穿电压为1200V、导通电阻为20mΩ、漏源电流为75 A、阈值电压为2.4V的4H-SiC DMOSFET.     

碳化硅MOSFET反型沟道迁移率的研究

SiC MOSFET是制作高速、低功耗开关功率器件的理想材料，然而，制作反型沟道迁移率较高的SiC MOSFET工艺尚未取得满意结果。通过在N0中高温退火可以显著地提高4H—SiC MOSFET的有效沟道迁移率；采用H2中退火制作的4H—SiC MOSFET阈值电压为3．1V，反型沟道迁移率高于100cm^2／Vs的栅压的安全工作区较宽。N20退火技术由于其的安全性而发展迅速并将取代N0。     

高温氧化对SiC MOS器件栅氧可靠性的影响

SiC金属氧化物半导体(MOS)器件中SiO2栅氧化层的可靠性直接影响器件的功能.为了开发高可靠性的栅氧化层,将n型4H-SiC (0001)外延片分别在1 200,1 250,1 350,1 450和1 550℃5种温度下进行高温干氧氧化实验来制备SiO2栅氧化层.在室温下,对SiC MOS电容样品的栅氧化层进行零时击穿(TZDB)和与时间有关的击穿(TDDB)测试,并对不同干氧氧化温度处理下的栅氧化层样品分别进行了可靠性分析.结果发现,在1 250℃下进行高温干氧氧化时所得的击穿场强和击穿电荷最大,分别为11.21 MV/cm和5.5×10-4 C/cm2,势垒高度(2.43 eV)最接近理论值.当温度高于1 250℃时生成的SiO2栅氧化层的可靠性随之降低.     

Extraction of SiO2/SiC interface trap profile in 4H- and 6H-SiC metal-oxide semiconductor field-effect transistors from subthreshold characteristics at 25°C and 150°C

The profile of trap density at the SiO₂/SiC interface in SiC metal-oxide semiconductor field-effect transistors (MOSFETs) is critical to study the channel electron mobility and evaluate device performance under various processing and annealing conditions. In this work, we report on our results in determining the interface trap density in 4H- and 6H-SiC MOSFETs annealed in dry O₂, NO, and CO₂, respectively, based on the device transfer and currentvoltage characteristics in the subthreshold region at 25°C and 150°C. We also studied electron field-effect mobility, fixed oxide charge, and gate leakage in those devices.     

SiO_2/SiC界面的Wet-ROA改性机理研究

高温热氧化法在4H-SiC(0001)晶面上生成SiO2氧化膜,采用湿氧二次氧化(wet-ROA)工艺对样品进行处理,通过测量SiCMOS结构界面电学特性,发现wet-ROA工艺有助于降低界面态密度,改善SiO2/SiC界面电学特性。采用变角X射线光电子能谱(ADXPS)技术对SiO2/SiC界面过渡区进行分析,通过过渡区厚度计算和过渡区成分含量比较,发现湿氧二次氧化工艺可减小过渡区氧化膜厚度,降低过渡区成分含量,进而揭示了降低SiO2/SiC界面态密度,改善界面电学特性的微观机理。     

Effect of processing conditions on inversion layer mobility and interface state density in 4H−SiC MOSFETs

N-channel, inversion mode MOSFETs have been fabricated on 4H−SiC using different oxidation procedures, source/drain implant species and implant activation temperature. The fixed oxide charge and the field-effect mobility in the inversion layer have been extracted, with best values of 1.8×10¹² cm⁻² and 14 cm²/V-s, respectively. The interface state density, D_it close to the conduction band of 4H−SiC has been extracted from the subthreshold drain characteristics of the MOSFETs. A comparison of interface state density, inversion layer mobility and fixed oxide charges between the different processes indicate that pull-out in wet ambient after reoxidation of gate oxide improves the 4H−SiC/SiO₂ interface quality.     

Electrical transport and current properties of rare-earth dysprosium Schottky electrode on p-type GaN at various annealing temperatures

The electrical and current transport properties of rapidly annealed Dy/p-GaN SBD are probed by I-V and C-V techniques. The estimated barrier heights (BH) of as-deposited and 200℃ annealed SBDs are 0.80 eV (I-V)/0.93 eV (C-V) and 0.87 eV (I-V)/1.03 eV (C-V). However, the BH rises to 0.99 eV (I-V)/ 1.18 eV(C-V) and then slightly deceases to 0.92 eV (I-V)/1.03 eV (C-V) after annealing at 300℃ and 400℃. The utmost BH is attained after annealing at 300℃ and thus the optimum annealing for SBD is 300℃. By applying Cheung''s functions, the series resistance of the SBD is estimated. The BHs estimated by I-V, Cheung''s and Ψ_S-V plot are closely matched; hence the techniques used here are consistency and validity. The interface state density of the as-deposited and annealed contacts are calculated and we found that the N_SS decreases up to 300℃ annealing and then slightly increases after annealing at 400℃. Analysis indicates that ohmic and space charge limited conduction mechanisms are found at low and higher voltages in forward-bias irrespective of annealing temperatures. Our experimental results demonstrate that the Poole-Frenkel emission is leading under the reverse bias of Dy/p-GaN SBD at all annealing temperatures.     

4H-SiC MOSFETs utilizing the H2 surface cleaningtechnique

The H₂ cleaning technique was examined as the precleaning of the gate oxidation for 4H-SiC MOSFETs. The device had a channel width and length of 150 and 100 μm, fabricated on the p-type epitaxial layer of 3×10¹⁶ cm^-3. The gate oxidation was performed after the conventional RCA cleaning, and H₂ annealing at 1000°C. The obtained channel mobility depends on the pre-cleaning process strongly, and was achieved 20 cm²/N s in the H₂ annealed sample. The effective interface-state density was also measured by the MOS capacitors fabricated on the same chips, resulting 1.8×10¹² cm^-2 from the photo-induced C-V method     

Excellent effects of hydrogen postoxidation annealing on inversionchannel mobility of 4H-SiC MOSFET fabricated on (112¯0) face

Effects of hydrogen postoxidation annealing (H₂ POA) on 4H-silicon carbide (SiC) MOSFETs with wet gate oxide on the (112¯0) face have been investigated. As a result, an inversion channel mobility of 110 cm²/Vs was successfully achieved using H₂ POA at 800°C for 30 min. H₂ POA reduces the interface trap density by about one order of magnitude compared with that without H₂ POA, resulting in considerable improvement of the inversion channel mobility to 3.5 times higher than that without H₂ POA. In addition, 4H-SiC MOSFET with H₂ POA has a lower threshold voltage of 3.1 V and a wide gate voltage operation range in which the inversion channel mobility is more than 100 cm²/Vs