An 80 ns 32K EEPROM using the FETMOS cell

A 32K bit EEPROM using the FETMOS (floating-gate electron tunneling MOS) cell has achieved a typical access time of 80 ns and a die size of 20.6 mm/SUP 2/ using approximately 3 /spl mu/m feature sizes. The device has many built-in ease of use and ease of test features, including multimode erase (word, page, and bulk), bulk `O' program, latched inputs for program and erase operation, nonlocked high voltage supply, and margin test capability for both programmed and erased states. A unique TPP (transparent-partial programming) yield enhancement technique, using polysilicon fuse programming, can convert partially good 32K dice into totally good 16K and 8K devices.     

An 8 ns 4 Mb serial access memory

A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 μm CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V     

An 80-ns 1-Mb flash memory with on-chip erase/erase-verifycontroller

An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ². The die area is 32.3 mm². An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor     

A 256 kbit ROM with serial ROM cell structure

The realization of a 256 kbit ROM using a 500 /spl Aring/ E/D NMOS technology is described. A high packaging density has been achieved by using a NAND structure in the memory array and in the decoders. Some characteristics of this serial ROM structure are discussed and compared with the conventional parallel configurations. The 32K/spl times/8 bit ROM with a bit size of 5.25/spl times/5.5 /spl mu/m/SUP 2/ has a total chip area of 18.6 mm/SUP 2/. Operating from a single 5 V supply, the device has a typical access time of 850 ns with a minimum cycle time of 1500 ns and dissipates 70 mW. In the power-down mode this power is reduced to 5 mW.     

An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate

Describes a fully decoded, TTL compatible, electrically alterable, 8-kbit MOS ROM using a two-level n-channel polysilicon gate process. The memory cell consists of a single transistor with stacked gate structure where the floating gate covers only one part of the channel and is extended to an erase overlap of the source diffusion region off the channel. Programming in typically 100 ms/word is achieved by injection of hot electrons from the short channel (3.5 /spl mu/m) into the floating gate. Electrical block erasure is performed by Fowler-Nordheim emission of electrons from the floating gate. To avoid excessive avalanche breakdown currents during erasure 40 nm-50 nm oxides at the erase overlap and a voltage ramp are used. The memory operates with standard voltages (/spl plusmn/5 V, +12 V), during read, program and erase operation, a single pulsed high voltage (+26 V) for programming, and an erase voltage ramp of +35 V maximum. Typical access time is 250 ns.     

基于WISHBONE总线的FLASH闪存接口设计

本文简要介绍了AMD公司Am29LV160D芯片的特点,并对WISHBONE总线作了简单的介绍,详细说明了FLASH memory与WISHBONE总线的硬件接口设计及部分Verilog HDL程序源代码。     

Electrically reprogrammable ROM using N-channel memory transistors with floating gate

An electrically reprogrammable read-only-memory (REPROM) device, providing the fully decoded and on-board-writable functions, is described. The device consists of novel N-channel memory transistors with floating gate, non-volatile memory transistors, which enable electrically reprogramming operation. The memory transistor has been through more than 10⁷ rewrite cycles with no gain facto (β) decrease. The memory device has been processed by the flat-MOS and the Si-gate technologies. It has a 2048 bit memory capacity, organized as 256 words of 8 bits. The polycrystalline silicon floating gate is covered with vapor-deposited silicon nitride. This allows selective write and erase operation, giving the memory device a new bit-level reprogrammable function.     

An experimental 1 Mbit DRAM based on high S/N design

The key to achieving 1-Mb is higher signal-to-noise ratio, while maintaining single 5-V operation even for small feature-size MOSTs. To meet this requirement, three developments are proposed: a corrugated capacitor (memory) cell, a multidivided data line structure, and an on-chip voltage limiter. The results include an improvement in signal-to-noise ratio by a factor of about 22 and provision for single 5-V operation. These techniques have been proven to be useful through the design and evaluation of an experimental 21-/spl mu/m/SUP 2/-cell, single-5-V, 1-Mb NMOS DRAM. Its significant features include: an access time of 90 ns, a power dissipation of 295 mW at 260 ns cycle time, and a 46 mm/SUP 2/ chip area.     

A submicron 1 Mbit dynamic RAM with a 4-bit-at-a-time built-in ECC circuit

A submicron CMOS 1-Mb RAM with a built-in error checking and correcting (ECC) circuit is described. An advanced bidirectional parity code with a self-checking function is proposed to reduce the soft error rate. A distributed sense circuit makes it possible to implement a small memory cell size of 20 /spl mu/m/SUP 2/ in combination with a trench capacitor technique. The 1M word/spl times/1 bit device was fabricated on a 6.4/spl times/8.2 mm chip. The additional 98-kb parity cells and the built-in ECC circuit occupy about 12% of the whole chip area. The measured access time is 140 ns, including 20 ns ECC operation.     

An experimental 512-bit nonvolatile memory with ferroelectricstorage cell

An experimental 512-b random-access memory based on ferroelectric-capacitor storage cells has been successfully fabricated and tested. The device was designed solely for use in process development and electrical characterization and includes onboard test circuitry for that purpose. The internal timing of the memory is controlled externally to allow experimentation with timing algorithms, hence the name 512 externally controlled device, or 512 ECD. The authors discuss the properties of the ferroelectric ceramics used in integrated circuit memories, the operation of a destructively read ferroelectric memory cell, and the organization of the 512 ECD die, including its onboard test circuitry. Finally, retention and wear-out properties of ferroelectric capacitors are discussed as they relate to design requirements     

An SRAM cell with nonvolatile memory for programmable logicapplications

A memory cell has been developed and fabricated that during normal operation acts as an SRAM cell. The state of the cell can be “saved,” and at power up, the cell can be put back into that state     

闪存技术打造手机安全新时代

随着通信产业的快速发展与成熟,手机正在成为一个多功能、不断给用户带来全新体验的"魔盒"--掌上游戏、移动影院、音乐空间、电子钱包、网上支付以及房屋和汽车钥匙等.     

A 256K HCMOS ROM using a four-state cell approach

A 256K HCMOS ROM design is discussed using a geometry-variable four-state cell for high packing density. Design, area, and process margin comparisons are made to other cell approaches. The architecture of the chip is shown and device performance is summarized. The 32K/spl times/8-bit ROM has typical access times of 200 ns with 11 mA of active current at 1000-ns cycle times and typical standby currents of 300 nA. Single-layer programming is performed with the poly layer, which is in the later stages of the process cycle than field-oxide or depletion implant programmed parts. The part is produced using an n-well HCMOS process with 2-/spl mu/m poly gate lengths. The part exhibits immunity from latchup without an epi substrate layer. This is primarily due to layout procedures to insure good substrate clamping and guardbanding.     

Compact model development for a new nonvolatile memory cell architecture

To facilitate the development of system-on-chip designs, accurate models are required for each of the new elements being included. In this paper, a new model for a novel low power flash memory device, the top floating gate cell, which can be integrated into CMOS processes with minimal disruption to the standard process is described.     

VDNROM: A novel four-physical-bits/cell vertical channel dual-nitride-trapping-layers ROM for high density flash memory applications

A novel vertical channel dual-nitride-trapping-layer ROM (VDNROM) flash memory with oxide–nitride–oxide–nitride–oxide (ONONO) dielectrics stack is proposed and experimentally demonstrated. Compared with the conventional planar NROM cell, since the cell area of the proposed vertical structure is independent of the gate length, the VDNROM structure can relax the limitation of the gate length scaling, and can have high capability of cell area shrinking. The fabrication process of this VDNROM device is basically compatible with planar CMOS technology. The VDNROM cell can be programmed and erased by the hot carrier injection to the localized trapping dual-nitride layers, so it can achieve a four-physical-bits storage capability each cell. The reliability behaviors including the cycling endurance and the bake retention at 150 °C have also been investigated and show the acceptable characteristics. The experiment results verify the VDNROM cell as a good candidate for high density applications.     

一种在DDS中节省ROM资源的实用方法

直接数字频率合成(DDS)是继直接频率合成和间接频率合成之后发展起来的第三代频率合成技术。主要介绍了一种可以大大节省FPGA和ASIC资源的DDS设计和实现方法。应用这种设计可以同时输出完全正交、高质量的SIN/COS信号。文章对DDS的构成原理、优化算法以及具体实现进行了详细的描述。     

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cellwith PMOS access transistors

While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 μm BiCMOS technology     

An asymmetric memory cell using a C-TFT for single-bit-line SRAM's

This paper proposes a compact single-bit line SRAM memory cell, which we call an asymmetric memory cell (AMC), using a complementary thin-film transistor (C-TFT). A C-TFT is composed of a top-gate n-channel TFT and a bottom-gate p-channel TFT. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4-μm design rules. Stable read and write operations under low-voltage can be realized by using a C-TFT     

A new low-power GaAs two-single-port memory cell

This paper describes an experimental static memory cell in GaAs MESFET technology. The memory cell has been implemented using a mix of several techniques already published in order to overcome some of their principal drawbacks related to ground shifting, destructive readout, and leakage current effects. The cell size is 36×37 μm² using a 0.6-μm technology. An experimental 32 word × 32 bit array has been designed. From simulation results, an address access time of 1 ns has been obtained. A small 8 word×4 bit protoype was fabricated. The cell can be operated at the single supply voltage from 1 up to 2 V. The evaluation is provided according to the functionality and power dissipation. Measured results show a total current consumption of 14 μA/cell when operated at 1 V     

An 800 Mbit/s optical transmission experiment using a single-mode fiber

It has been confirmed by a preliminary transmission experiment that a repeater spacing at 800 Mbits/s can be lengthened up to 7.3 km, by using a combination of a low-loss single-mode fiber and a well designed AlGaAs laser. The laser is modulated by a signal current superimposed on a dc bias current above the threshold. This modulation scheme avoids the spectrum broadening of the laser at the cost of extinction ratio degradation. A discrepancy of about 13 dB exists between the measured and the calculated error-rate performance curves. The major part of the discrepancy, 10 dB, is due to the extinction ratio degradation.