RF MEMS开关封装的通孔工艺研究

将喷胶技术应用到金属互联工艺中,此方法可以用于器件的封装。具体工艺步骤如下:在衬底与硅帽键合结束后在底部湿法刻蚀孔200μm。在孔中利用PECVD生长SiO2,优化喷胶工艺在盲孔底部进行光刻,RIE除去SiO2后电镀金与衬底正面器件实现金属互联,传输线从衬底底部引出。针对整个流程中关键的步骤,进行20μm深孔光刻实验,结果证实能在深孔中光刻图形。     

等离子体刻蚀过程中的FTIR监控技术

采用傅里叶红外光谱仪(FHR)和MCT红外探测器可以构成原位的FTIR测量系统,可应用于在电感耦合等离子体刻蚀机中进行的硅刻蚀工艺.文中对反应腔室腔壁状态对刻蚀过程的影响,以及在硅晶片表面反应层的变化进行了详细的研究.实验表明:采用含F化合物对反应腔室进行清洗会改变反应腔室的状态,在腔室内壁状态达到稳定之前会对刻蚀速率的一致性造成扰动.硅片表面反应层中的化学组成变成了以CF为主的薄膜层,对刻蚀过程的有一定的抑制作用.     

高深宽比倾斜沟槽的深硅刻蚀技术

针对微电子机械系统(MEMS)行业对3D加工日益增长的需求,提出了一种结合法拉第笼和倾斜衬底支架,利用改进的BOSCH工艺进行任意角度深硅刻蚀的创新工艺方案。首先通过仿真计算对法拉第笼的特征尺寸进行了优化,进一步采用法拉第笼和用于制备倾角的衬底支架,对BOSCH工艺参数进行了调整,最终获得了倾角为30°、深度超过25μm、深宽比高达7.9∶1的倾斜沟槽。结果表明利用法拉第笼和倾斜衬底支架,采用深硅刻蚀工艺可以制备高深宽比的倾斜沟槽,而且沟槽角度可以通过加工不同倾角的支架实现。结合法拉第笼和倾斜衬底支架进行等离子体刻蚀可为其他倾斜结构的制备工艺提供参考。     

无掩模硅图形衬底上3C-SiC的异质外延生长

采用低压化学气相沉积方法在无掩模的硅图形衬底上异质外延生长3C-SiC.硅图形衬底采用光刻和ICP刻蚀得到.图形由平行长条状沟槽和台面组成,其中沟槽宽度为1～10μm不同间隔,沟槽之间距离为1～10μm不同间隔.对于在不同的沟槽和台面尺寸区域3C-SiC的生长进行了详细研究.采用扫描电镜分别观察了不同区域的生长形貌,分析了图形衬底结构上SiC的生长行为.其中合并生长形成的空气隙结构可以释放由Si和SiC晶格失配引起的应力,从而可以用来解决SiC生长中的晶片翘曲问题,进行厚膜生长.XRD结果表明此无掩模硅图形衬底上得到3C-SiC(111)取向生长.     

高深宽比硅通孔的SAPS兆声波清洗技术

硅通孔(TSV)是三维系统集成的关键技术和发展趋势,目前已经可以实现深宽比为10∶1的TSV结构,且向着更高深宽比方向发展。在TSV制造工艺中,硅通孔刻蚀后的清洗是目前的关键技术难点之一。针对TSV刻蚀的工艺特点和TSV结构的特点,基于气体交替技术的硅刻蚀反应副产物种类以及清洗过程清洗液在TSV孔内的流体特性进行分析,探讨了一种基于现有清洗液,利用空间交变相位移(SAPS)兆声波技术进行TSV刻蚀后的清洗方法,并阐述了该清洗工艺的特点及前后工艺间的相互影响。研究结果表明,SAPS兆声波清洗能高效去除深孔内刻蚀残余产物,在TSV工艺集成中有较好的应用前景。     

无掩模硅图形衬底上3C-SiC的异质外延生长

采用低压化学气相沉积方法在无掩模的硅图形衬底上异质外延生长3C-SiC.硅图形衬底采用光刻和ICP刻蚀得到.图形由平行长条状沟槽和台面组成,其中沟槽宽度为1～10μm不同间隔,沟槽之间距离为1～10μm不同间隔.对于在不同的沟槽和台面尺寸区域3C-SiC的生长进行了详细研究.采用扫描电镜分别观察了不同区域的生长形貌,分析了图形衬底结构上SiC的生长行为.其中合并生长形成的空气隙结构可以释放由Si和SiC晶格失配引起的应力,从而可以用来解决SiC生长中的晶片翘曲问题,进行厚膜生长.XRD结果表明此无掩模硅图形衬底上得到3C-SiC(111)取向生长.     

准分子激光电化学刻蚀硅的刻蚀质量研究

为了解决现有硅刻蚀工艺中存在的刻蚀质量等问题,采用激光加工技术和电化学加工技术相结合的工艺对硅进行了刻蚀,研究了该复合工艺的工艺特性。实验中采用248nm-KrF准分子激光作光源聚焦照射浸在KOH溶液中的阳极n-Si上,实现激光诱导电化学刻蚀。在实验的基础上,研究了激光电化学刻蚀Si的刻蚀孔的基本形貌,并对横向刻蚀和背面冲击等质量问题进行了分析。结果表明,该工艺刻蚀的孔表面质量好、垂直度高;解决了碱液中Si各向异性刻蚀的自停止问题,具有加工大深宽比微结构的能力;也具有不需光刻显影就能进行图形加工的优越性。     

射频溅射刻蚀反射栅条

本文介绍用射频溅射刻蚀的方法在LiNbO_3晶片上刻蚀声表面波器件的反射沟槽,并获得性能较好的反射栅色散延迟线(不加权)。本文重点介绍射频溅射刻蚀LiNbO_3晶片要解决的几个工艺问题,即脱氧、再淀积,掩模材料的选择。还讨论了刻蚀的沟槽陡度,均匀性和重复性等问题。     

清洗工艺在太阳能电池工业化生产中的应用

太阳能电池工业化生产中采用前清洗工艺,可以有效地去除硅片表面的机械损伤层,清除表面油污和金属杂质,形成起伏不平的绒面进而增加对太阳光的吸收,增加PN结面积,最终提高硅晶体太阳电池的光电转换效率。后清洗工艺可以有效地进行湿法刻蚀和去除在扩散过程中形成的PSG。     

LED用蓝宝石晶片湿法腐蚀清洗技术的研究

介绍了蓝宝石晶片的清洗原理：通过分析蓝宝石的表面净化原理和对湿法腐蚀清洗工艺试验的研究,提出了一种适用于工业化生产蓝宝石晶片的清洗剂和净化工艺,满足了LED领域的蓝宝石晶片表面洁净度要求。     

视觉系统在硅片检测上的应用

机器视觉是利用机器代替人眼来做各种测量和判断.介绍了全自动硅片装片机中利用视觉系统对硅片的边缘进行检测,在线将有缺陷的硅片剔除,将完好的硅片送入下一个环节.大大降低了人工强度和碎片率,减少了人工与硅片的接触,避免了人为因素对硅片的污染,有效地提高了成品率.     

0.13μm铜互连工艺鼓包状缺陷问题的解决

传统集成电路制造工艺主要采用铝作为金属互连材料,但是随着晶体管尺寸越来越小,在0.13μm及以上制程中,一般采用铜大马士革互连工艺来提高器件的可靠性。铜互连工艺中需要用氮化硅作为穿孔图形蚀刻的阻挡层,由于氮化硅材质具有很强的应力,再加上制程中的热反应和蚀刻效应就会造成氮化硅层从界面掀起从而形成一种鼓包状缺陷(bubble defect)。文章通过调整并控制铜金属连线层间氧化电介质层的蚀刻速率,改变有机介质层(BARC)的沉积方法,以及改进产品的电路设计的检验规则,从而解决鼓包状缺陷的产生,降低产品芯片的报废率,提高产品的良率。     

工艺参数对Si深槽刻蚀的影响

采用Bosch技术研究了在Si深槽刻蚀中刻蚀/钝化比、刻蚀阶段钝化气体保护时间、刻蚀和钝化工艺重叠时间等工艺参数对刻蚀结果的影响。通过不同工艺条件的试验,发现刻蚀钝化比是影响侧壁结构的主要因素,其大小直接影响了深槽的垂直度;适当增加刻蚀阶段钝化气体通入时间对减小线宽损失有很大的作用,但增加过多会产生长草效应;合适的刻蚀和钝化工艺重叠时间,不仅可以减小侧壁表面的起伏度,还可以一定程度上减小线宽损失。采用刻蚀/钝化比为7:5、刻蚀阶段钝化气体通入时间为25min、刻蚀、钝化工艺重叠时间分别为0.5、1s的工艺条件,成功地实现了一个垂直度达(90±0.1)°、深40μm、线宽损失小于50nm的Si深槽刻蚀结构。     

Particle removal from silicon wafer surface in wet cleaning process

Particle removal from silicon wafer surfaces was studied using acid and alkaline solutions employed in wet cleaning processes found in semiconductor manufacturing. It was demonstrated that alkaline solutions are superior to acid solutions in terms of particle removal efficiency. The following particle removal mechanism in the alkaline solutions was confirmed: the solutions etch the wafer surfaces to lift off particles, and the particles are then electrically repelled by the wafer surfaces. It was determined experimentally that an etch rate of 0.25 nm/min or more is required to lift off the particles adsorbed on the wafer surfaces. It was also confirmed that when the pH value of NH₄OH-H₂O₂-H₂O solution becomes higher, polystyrene latex spheres and natural organic particles are oxidized, with their surface turning into a gel and their shape changing. The particle removal efficiency was demonstrated to be degraded by the oxidation of organic particles. The results suggest that the mixing ratio of the NH₄OH-H₂O₂-H ₂O solution should be set at 0.05:1:5     

Isotropic wet chemical etching of deep channels with optical surface quality in silicon with HNA based etching solutions

Online trace analysis based on UV/Vis spectroscopy requires long detection paths. Therefore an isotropic wet etch process in silicon is developed to fabricate a 300 µm deep channel with low channel wall roughness for desired light guidance application. Four etchant compositions were compared in terms of etching rate, surface roughness and selectivity in a beaker process. The best fitting mixture was selected. To further increase the surface quality (bubble issue) a spin etcher tool is used for producing the channels. The dependence of homogeneity and defect density on media flux, and rotation velocity was investigated. Results show that high rotation velocity and high media flux lead to great defects in the channel wall. Through rotation of the wafer during etching, the etching rate of silicon rises compared to the beaker process due to the rapid removal of etch products and simultaneous supply of fresh etchant. After 38 min of etching, 300 µm deep semi-circular channels with high optical quality (Rq=10 nm±2 nm) over 3 m were produced.     

Process optimization of a deep trench isolation structure for high voltage SOI devices

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail.An optimized trench process is also proposed.It is found that there are two main reasons:one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect;and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom.In order to improve the isolation performance of the deep trench,two feasible ways for optimizi...     

Process optimization and characterization of silicon microneedles fabricated by wet etch technology

In this research, we have optimized a fabrication technique for manufacturing microneedle arrays in standard silicon wafer ((100) orientation) using potassium hydroxide (KOH) wet etching. The etch behaviour of silicon was simulated for different mask shapes and sizes using SIMODE software. In the context of the fabrication process, we demonstrate the influence of the mask design and the processing environment such as etching parameters and etch bath conditions on the formation of silicon microneedle structures (needle height up to 300 μm) and its reproducibility. Single needle shear tests have been carried out to characterize the mechanical stiffness of fabricated microneedles.     

RMOS器件中硅槽及多晶硅栅的刻蚀

ＲＭＯＳ（Ｒｅｃｔａｎｇｕｌａｒ Ｇｒｏｏｖｅｄ ＭＯＳ）器件因具有独特的性能而得到较好的应用。本文介绍用ＲＩＥ设备进行ＲＭＯＳ器件硅槽刻蚀的工艺，并对填满硅槽内的多晶硅栅的刻蚀亦作了研究。选择适当的工艺条件，可刻蚀出形貌较好的硅槽，并可在刻蚀完多晶硅后保持硅槽内多晶硅栅形貌完好 。     

Nearly bird's beak-free local oxidation technology for controlled dielectric formation in deep silicon trenches

Silicon deep trench isolation technology using local oxidation is reported. Scaled, high-density trench capacitors were fabricated with varying trench aspect ratios. Nearly bird's beak-free local oxidation resulted in a controlled growth of silicon dioxide on the trench bottom surfaces and significantly improved the trench gate MOS isolation characteristics. Detailed MOS capacitance measurements were performed and wafer yield in excess of 90% was demonstrated across 4 inch diameter silicon wafers.<>     

三维掩膜硅各向异性腐蚀工艺释放微悬空结构

提出了一种新颖的基于三维掩膜的硅各向异性腐蚀工艺,即利用深反应离子刻蚀、湿法腐蚀等常规体硅刻蚀工艺和氧化、化学气相沉积(CVD)等薄膜工艺制作出具有三维结构的氧化硅(SiO2)或氮化硅(Si3N4)薄膜,以该三维薄膜作为掩膜进行各向异性腐蚀,该工艺可以应用于MEMS微悬空结构的制作。利用该工艺成功地在单片n-Si(100)衬底上完成了一种十字梁结构的释放,并对腐蚀的过程和工艺参数进行了研究。