Electrical stress on irradiated thin gate oxide partially depleted SOI nMOSFETs

The effect of hot-carrier stress on 60 MeV proton irradiated thin gate oxide partially depleted SOI nMOSFETs has been studied. The results are compared with those from the electrical stress of non-irradiated devices. Whereas no significant differences are observed for the front channel degradation, hot-electron trapping in the buried oxide is found to be enhanced in the irradiated devices. This hot-electron trapping leads to a compensation or neutralization of the effects caused by the radiation-induced positive trapped charges. It is shown that a similar hot-electron trapping enhancement can be achieved in non-irradiated devices stressed under certain back gate bias conditions.     

Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 /spl mu/m CMOSFET with 2-nm thin gate oxide

Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BC-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 /spl mu/m with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition of the 0.1 /spl mu/m FB-SOI pMOSFET is similar to that of the 0.1 /spl mu/m BC-SOI pMOSFET.     

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a “C” shape of the threshold voltage corresponding with the second peak in the gm curve.     

Gate-induced floating body effect excess noise in partially depleted SOI MOSFETs

Low frequency excess noise associated to gate-induced floating body effect is for the first time reported in Partially Depleted SOI MOSFETs with ultrathin gate oxide. This was investigated with respect to floating body devices biased in linear regime. Due to a body charging from the gate, a Lorentzian-like noise component superimposes to the conventional 1/f noise spectrum. This excess noise exhibits the same behavior as the Kink-related excess noise previously observed in Partially Depleted devices in saturation regime.     

阶梯栅氧结构的NLDMOS热载流子效应研究

本文对一种新型的阶梯栅氧结构的NLDMOS（Step Gate Oxide NLDMOS , SG-NLDMOS）的热载流子效应进行了研究。采用直流电压应力实验、TCAD仿真、电荷泵测试等方法,对退化现象进行了分析,并提出了退化机制。然后研究了漂移区注入剂量对器件热载流子效应的影响,结果表明低的漂移区注入剂量可以更有效地减小器件导通电阻的退化。     

Hot-carrier-induced on-resistance degradation of step gate oxide NLDMOS

The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS(SG-NLDMOS) transistors are investigated in detail by a DC voltage stress experiment,a TCAD simulation and a charge pumping test.For different stress conditions,degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented.Then the effect of various doses of n-type drain drift(NDD) region implant on R_(on) degradation is investigated.Experimental results show that a lower NDD dosage can redu...     

Effects of floating body on double polysilicon partially depleted SOI nonvolatile memory cell

The floating-body effect of nonvolatile memory cells fabricated using partially depleted silicon-on-insulator (SOI) technology has been investigated using two-dimensional numerical device simulation. Compared with similar bulk devices, the floating-body effect of partially depleted SOI MOSFETs introduces instability in the value of the drain current during sensing and extra hot-electron gate current in programming. The effects of the drain-current instability on the error margins in read operation are studied. The floating-body effect is found to be heavily dependent on biasing condition.     

Temperature dependence of hot-carrier-induced degradation in 0.1μm SOI nMOSFETs with thin oxide

This letter investigates hot-carrier-induced degradation on 0.1 μm partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI devices exhibits inverse temperature dependence compared to that of BC-SOI devices. This is attributed to the floating-body effect (FBE) and parasitic bipolar transistor (PBT) effect     

Impact on the back gate degradation in partially depleted SOI n-MOSFETs by 2-MeV electron irradiation

Degradation of the electrical performance in partially depleted SOI MOSFETs by 2-MeV electrons is presented. The degradation behavior of the 2^nd transconductance (g_mf) peak and its dependence on the back gate voltage is discussed taking into account the degradation of the back gate. The drain current in the subthreshold region is increased by irradiation. This is caused by the turn-on of the parasitic edge transistor. The 2^nd peak in the transconductance (g_mf) tends to decrease after irradiation, while less degradation is observed in the 1^st g_mf peak. The decrease of the 2^nd g_mf peak enhances by the application of a negative V_BG and the result can be explained by the degradation of the Si/buried oxide interface and the increase of the sidewall leakage, which gives rise to a lowering of the body potential.     

Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits

This paper presents a new circuit technique to alleviate the uncontrollable floating-body-induced hysteretic component present in the transfer characteristics of voltage-mode CMOS Schmitt trigger circuits in a partially depleted silicon-on-insulator technology. This technique integrates a successive switching threshold shift mechanism with the systematic body contact scheme, resulting in improved noise immunity and well-defined hysteresis behavior for the Schmitt trigger circuit that is suitable for use as a low-noise receiver, level shifter, waveform-reshaping circuit, and delay element in very large-scale integrated applications.     

Modeling for floating body effects in fully depleted SOI MOSFETs

A model based on SOI MOSFET and BJT device theories is developed to describe the current kink and breakdown phenomena in thin-film SOI MOSFET drain-source current-voltage characteristics operated in strong inversion. The modulation of MOSFET current by raised floating body potential is discussed to provide an insight for understanding the suppression of current kink in fully depleted thin-film SOI devices. The proposed analytical model successfully simulates the drain current-voltage characteristics of thin-film SOI n-MOSFETs fabricated on SIMOX wafers     

Radiation source dependence of performance degradation in thin gate oxide fully-depleted SOI n-MOSFETs

The degradation of the electrical performance of thin gate oxide fully depleted SOI n-MOSFETs and its dependence on the radiation particles are investigated. The transistors are irradiated with 7.5-MeV protons and 2-MeV electrons at room temperature without bias. The shift of threshold voltage and the coupling effect with the degraded opposite gate are clarified. A remarkable reduction of the floating body effects is observed after irradiation. The degradation of the extracted parameters is discussed by a comparison with the damage coefficients.     

Hot-carrier-induced degradation of gate dielectrics grown innitrous oxide under accelerated aging

Gate oxides grown with partial and complete oxidation in N₂ O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g_m had a 15×improvement over control oxides not grown in a N₂O atmosphere. Further improvement in g_m degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO₂ interface, leading to lower interface state generation (ISG). Improvements were also observed in I_g-V_g characteristics, indicating a reduction of trap sites both at the Si/SiO₂ interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N₂O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N ₂O oxides and is a subject for further study     

A new lifetime characterization technique using drain current transients in SOI material

A new technique based on the transient operation of the pseudo-MOS transistor is proposed for direct evaluation of generation lifetime and surface velocity in SOI wafers. The main advantages of the proposed technique are: (i) in situ operation (no prior processing of a transistor), (ii) set-up simplicity, (iii) fast comparison of different SOI technologies and (iv) simple identification of Si-film conductivity type. The influence of the electrical and non-electrical parameters of this technique is systematically investigated. Various SOI wafers (SIMOX and UNIBOND) are compared.     

A comparison of floating-body potential in H-gate ultrathin gate oxide partially depleted SOI pMOS and nMOS devices based on 90-nm SOI CMOS process

Based on a 90-nm silicon-on-insulator (SOI) CMOS process, the floating-body potential of H-gate partially depleted SOI pMOS and nMOS devices with physical gate oxide of 14 /spl Aring/ is compared. For pMOS devices, because the conduction-band electron (ECB) tunneling barrier is lower (/spl cong/3.1 eV), the ECB direct-tunneling current from the n/sup +/ poly-gate beside the body terminal will contribute to a large amount of electron charges into the neutral region and dominate the floating-body potential under normal operations. Conversely, owing to the higher valence-band hole tunneling barrier (/spl cong/4.5 eV), the floating-body potential of nMOS devices is dominated by the band-to-band-tunneling mechanism at the drain-body junction, not the direct-tunneling mechanism.     

Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs

A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs. Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out. Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs. The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.     

AC floating body effects in partially depleted floating body SOInMOS operated at elevated temperature: an analog circuitprospective

AC floating body effects in PD SOI nMOSFETs operated at high temperature are investigated. Both source/body and drain/body junction diode characteristics are greatly influenced by temperature, significantly impacting the ac kink effect as well its low-frequency (LF) noise characteristics. This is especially true for the pre-dc kink operation at high temperature. The increase of junction thermal generation current becomes an important body charging source and induces the LF Lorentzian-like excess noise     

Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI

This study compares the reliability of nMOSFETs with low- and high-doped ultra-thin body and buried oxide (UTBB) with fully depleted (FD) and partially depleted (PD) silicon on insulator (SOI). The high-doped devices display lower off-current leakage performance but more degradation in both hot-carrier stress (HCS) and positive bias temperature instability (PBTI) test at both room temperature and elevated temperature compared with the low-doped devices. The PBTI test indicates that the high-doped devices induce high tunneling leakage and that the degradation is highly associated with temperature. The degradation stabilizes with an increase in stress time. The thinner PD-SOI demonstrates low variation at the threshold voltage and low drive current under HCS. The FD-SOI has better drain leakage control than the PD-SOI.     

Characteristics and physical mechanisms of positive bias and temperature stress-induced drain current degradation in HfSiON nMOSFETs

Drain current degradation in HfSiON gate dielectric nMOSFETs by positive gate bias and temperature stress is investigated by using a fast transient measurement technique. The degradation exhibits two stages, featuring a different degradation rate and stress temperature dependence. The first-stage degradation is attributed to the charging of preexisting high-k dielectric traps and has a log(t) dependence on stress time, whereas the second-stage degradation is mainly caused by new high-k trap creation. The high-k trap growth rate is characterized by two techniques, namely 1) a recovery transient technique and 2) a charge-pumping technique. Finally, the effect of processing on high-k trap growth is evaluated.