共查询到20条相似文献,搜索用时 15 毫秒
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在越来越复杂的SoC芯片验证开发中,ABV(基于断言的验证)已经成为一种先进且有效的验证方法。SVA(System Verilog断言)是一种基于描述性的验证语言,它作为System Verilog语言的一个子集已成为IEEEl800标准。本文以AMBAAPB总线上的IIC总线控制器为例,简要介绍了利用VMM验证方法学来快速搭建以覆盖率为指导、约束随机化、可重用的分层验证平台。在此基础上详细阐述了在DUT的外部接口上绑定SVA断言检查器,从而在黑盒的条件下完成高效的功能验证。 相似文献
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Muhammad Waseem Anwar Muhammad Rashid Farooque Azam Muhammad Kashif 《Design Automation for Embedded Systems》2017,21(1):1-36
Model Based System Engineering (MBSE) is a renowned approach in the context of embedded systems development. It is frequently used to deal with the structural and behavioral aspects of system design. However, the verification of system design is generally performed in isolation. It is particularly true in the context of assertion based verification. Consequently, there is a huge gap between system design and its verification that seriously effects the productivity and time-to market objectives. Therefore, in this research, we target to reduce this gap by exploiting the features of MBSE and SystemVerilog assertions (SVA’s). This article introduces a novel MBSE approach to model the design verification aspects of embedded systems, along with the system design (structural and behavioral aspects). We propose SystemVerilog in Object Constraint Language (SVOCL), an OCL temporal extension for SystemVerilog, to represent the design verification requirements by means of SVA’s. As a part of research, SVOCL transformation engine has been developed to generate SVA’s code in order to automate the design verification of embedded systems. The application of SVOCL has been validated through four case studies. 相似文献
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传统的验证平台编写复杂,且难以在不同设计之间重用。采用SystemVerilog支持的VMM验证方法学,并结合带约束的随机验证和覆盖率驱动的验证技术,构建可重用验证平台,完成对UART模块的验证。与直接测试方法相比,该验证平台不仅能够有效提高验证效率,而且在模块级和系统级验证过程中,能够重用该验证平台或验证组件。 相似文献
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随着SystemVerilog成为IEEE的P1800规范,越来越多的项目开始采用基于SystemVerilog的验证方法学来获得更多的重用扩展性、更全面的功能覆盖率,以及更合理的层次化验证结构。本文主要提出了一种基于SystemVerilog的VMM验证方法学的验证环境。在这个验证环境中,验证了一个8位的MCU,这个MCU主要应用在数据卡项目中,主要特点是时钟周期与指令周期相等,并且相对于标准MUC指令需要时钟周期较少。通常验证MCU都会应用以前的16进制代码读入ROM中,通过仿真观察波形以及输出来确认功能正确,每次只能根据实际应用程序测试对应的一部分MCU功能,缺少一个量化的指标,而且每次改动MCU,需要重新检查结果,效率比较低,而且验证质量无法保证。这里实现了用SystemVerilog来搭建一个基于VMM验证方法学的可移植、重用、扩展、完全自动检查、具有层次化结构的MCU验证平台。这里运用了VMM方法学,设计了一个层次化的验证结构,可以较简单地移植并验证其他类型的MCU,抽象了MCU指令,并且通过约束产生随机指令激励,可以实现遍历所有指令以及地址,另外功能覆盖率模型帮助能够收集并监测覆盖率。 相似文献
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基于断言语言SVA的设计验证方法 总被引:1,自引:0,他引:1
基于断言SVA的验证是一种有价值的主流验证技术。断言特别适合于描述时序特性和因果特性。作为Sys-tem Verilog的重要组成部分,SVA提供了丰富的断言指令,能有效地提高验证测试工作的质量和效率。在此,首先介绍断言验证语言SVA,通过与Verilog验证对比,说明SVA在时序特性和因果特性验证上的优势,证明基于断言的验证是SoC设计验证的一种有效方法,能够有效地提高验证效率。 相似文献
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在介绍译码器工作原理的基础上,介绍了用VHDL语言实现译码器的设计方案,给出了用VHDL语言实现译码器的源程序,并用Max+plusII工具软件对其进行了模拟仿真验证。 相似文献
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Vemuri R. Kalyanaraman R. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1995,3(2):201-214
A method for generation of design verification tests from behavior-level VHDL programs is presented. The method generates stimuli to execute desired control-flow paths in the given VHDL program. This method is based on path enumeration, constraint generation and constraint solving techniques that have been traditionally used for software testing. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements, and wait statements which are not found in traditional software programming languages. Our model of constraint generation is specifically developed for VHDL programs with such constructs. Control-flow paths for which design verification tests are desired are specified through certain annotations attached to the control statements in the VHDL programs. These annotations are used to enumerate the desired paths. Each enumerated path is translated into a set of mathematical constraints corresponding to the statements in the path. Methods for generating constraint variables corresponding to various types of carriers in VHDL and for mapping various VHDL statements into mathematical relationships among these constraint variables are developed. These methods treat spatial and temporal incarnations of VHDL carriers as unique constraint variables thereby preserving the semantics of the behavioral VHDL programs. Constraints are generated in the constraint programming language CLP(R) and are solved using the CLP(R) system. A solution to the set of constraints so generated yields a design verification test sequence which can be applied for executing the corresponding control path when the design is simulated. If no solution exists, then it implies that the corresponding path can never be executed. Experimental studies pertaining to the quality of path coverage and fault coverage of the verification tests are presented 相似文献
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调试系统的设计和验证是多核SoC设计中的重要环节。基于某双核SoC的设计,提出一个片上硬件调试构架,利用FPGA构建该调试系统的硬件验证平台。双核SoC调试系统验证平台利用System Verilog DPI,将RealView调试器、Keil C51及目标芯片的验证testbench集成在一起,实现了双核SoC调试系统的RTL级调试验证。利用该平台,在RTL仿真验证阶段可方便地对ARM和8051核构成的双核SoC进行调试,解决仿真中出现的问题,从而有效缩短设计周期,并提高验证效率。该双核SoC调试系统验证平台的实现对其他系统芯片设计具有一定的参考价值。 相似文献
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The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using function declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioural VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ring-counter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach. 相似文献
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可编程逻辑器件的VHDL设计技术及其在航空火控电子设备中的应用 总被引:1,自引:1,他引:0
简要介绍了可编程逻辑器件CPLD和FPGA的结构和特点,着重介绍了VHDL语言的特点及选择VHDL的理由。通过几个实际应用中碰到的问题,介绍了使用VHDL的一点体会。最后,给出了一个成功应用VHDL设计的机械设备及其带来的优点。 相似文献