Experimental results on the integration of copper and CVD ultra low k material

The integration of ultra low k materials in copper damascene architecture is one of the main issues in finding microelectronic-process-compatible dielectric materials. The aim of this paper is to show the integration conformity with common equipment and process steps using a PECVD (plasma enhanced chemical vapor deposition) CF polymer ultra low k material in a Cu single damascene architecture (Proceedings of the Advanced Metallization Conference, 2002). The intermetal dielectric low k material used in the described structures has 2.1≤k≤2.3 (k depends on deposition process parameters [Microelectron. Eng. 50 (2000) 7–14]) and the copper was deposited by a metal organic chemical vapor deposition process. After chemical mechanical polishing the structures were characterized by scanning electron microscopy and electrical measurements.     

Integration and characterization of gas cluster processing for copper interconnects electromigration improvement

Basic physical properties as well as electrical and reliability performance of Infusion™ processing were evaluated. This approach, proposed as an alternative to CuSiN and electrolessly deposited Co-alloys, was shown to join the benefits of these two techniques without well-known associated drawbacks. Indeed, it is a uniform process, acting as an efficient Cu diffusion barrier, which does not require specific integration development. Different processes were introduced in a multi-level interconnect stack using ULK/USG stack as IMD, showing excellent electrical properties, and three times electromigration time-to-failure improvement with respect to standard SiCN barrier. However, it was shown that existing process conditions lead to some introduction of N atoms into ULK dielectric, showing there is still some room for process optimization in architectures using un-capped ULKs, to keep the benefits of EM improvement and aggressive effective dielectric constant.     

BNT陶瓷低温烧成与性能

采用复合添加BaCuO_2-CuO(以下简称BCC)、ZnO-B_2O_3-SiO_2(以下简称ZBS)等烧结助剂的方法,研究了Ba_4(Nd_(0.85)Bi_(0.15))_(28/3)Ti_(18)O_(54)陶瓷(以下简称BNT)低温烧结的烧结特性和微波介电性能。结果表明:复合添加(均为质量分数)2.5％BaCuO_2-CuO和5％ZnO-B_2O_3-SiO_2后可以在1050℃烧结成致密瓷,气孔率为5.73％,在5.6 GHz,相对个电常数ε_r为64.25,Q·f值为2026 GHz,频率温度系数τ_f为+26.4×10~(-6)℃~(-1),可望实现与Cu电极浆料低温共烧。     

Copper-dielectric cap interface with enhanced reliability for 45 nm technology and beyond

A production capable preparation of a Cu-dielectric cap interface with a significantly enhanced reliability robustness has been developed for the 45 nm dual damascene technology and beyond. The electromigration (EM) lifetime could be improved by a factor of 2 with an advanced in situ cleaning process (ACP) including a soft silicidation step of the Cu metallization prior to the Cu-cap deposition. The increase of the Cu metal line resistivity can be controlled and limited to <6%. Anneal experiments at high temperature underline a high thermal stability of the Cu-cap interface including the copper-silicide (CuSi) intralayer. The new ACP is applicable to Cu interconnects built with dense or porous ultra-low-k (ULK) dielectrics because the process minimizes the surface damage. This yields in a doubled dielectric breakdown strength of a Cu damascene structure with a ULK inter-level dielectric by implementation of the ACP.     

Modification of porous ultra-low K dielectric by electron-beam curing

The impact of electron irradiation on ultra-low K (ULK) porous dielectric material used in advanced interconnects is analyzed using spectroscopic and electrical characterizations. The e-beam irradiation modifies the chemical composition, the porosity and the optical indexes. The effects of e-beam curing on electrical properties and dielectric reliability are also evaluated.     

32nm CMOS工艺技术挑战

根据国际半导体技术发展蓝图(international technology roadmap for semiconductor,ITRS),CMOS技术将于2009年进入32nm技术节点.然而,在CMOS逻辑器件从45nm向32nm节点按比例缩小的过程中却遇到了很多难题.为了跨越尺寸缩小所带来的这些障碍,要求把最先进的工艺技术整合到产品制造过程中.文中总结并讨论了可能被引入到32nm节点的新的技术应用,涉及如下几个方面:浸入式光刻的延伸技术、迁移率增强衬底技术、金属栅/高介电常数栅介质(metal/high-k,MHK)栅结构、超浅结(ultra-shallow junction,USJ)以及其他应变增强工程的方法,包括应力邻近效应(stress proximity effect,SPT)、双重应力衬里技术(dualstress liner,DSL)、应变记忆技术(stress memorization technique,SMT)、STI和PMD的高深宽比工艺(high aspect ratio process,HARP)、采用选择外延生长(selective epitaxial growth,SEG)的嵌入SiGe(pFET)和SiC(nFET)源漏技术、中端(middle of line,MOL)和后端工艺(back-end of line,BEOL)中的金属化以及超低k介质(ultra low-k,ULK)集成等问题.     

32nm CMOS工艺技术挑战

根据国际半导体技术发展蓝图（international technology roadmap for semiconductor, ITRS) , CMOS技术将于2009年进入32nm技术节点. 然而,在CMOS逻辑器件从45nm向32nm节点按比例缩小的过程中却遇到了很多难题. 为了跨越尺寸缩小所带来的这些障碍,要求把最先进的工艺技术整合到产品制造过程中. 文中总结并讨论了可能被引入到32nm节点的新的技术应用,涉及如下几个方面：浸入式光刻的延伸技术、迁移率增强衬底技术、金属栅/高介电常数栅介质（metal/high-k, MHK）栅结构、超浅结（ultra-shallow junction, USJ）以及其他应变增强工程的方法,包括应力邻近效应（stress proximity effect, SPT) 、双重应力衬里技术（dual stress liner, DSL) 、应变记忆技术（stress memorization technique, SMT) 、STI和PMD的高深宽比工艺（high aspect ratio process, HARP) 、采用选择外延生长（selective epitaxial growth, SEG）的嵌入SiGe (pFET）和SiC (nFET）源漏技术、中端（middle of line, MOL）和后端工艺（back-end of line, BEOL）中的金属化以及超低k介质（ultra low-k, ULK）集成等问题.     

Sidewall restoration of porous ultra low-k dielectrics for sub-45 nm technology nodes

Plasma ashing and etching integration steps on porous ultra low-k (ULK) have been investigated and are found to damage the porous dielectric structural and electrical properties, leading to weak performance and reliability. In order to overcome these integration issues, an ULK restoration step is proposed. This work discuss the effect of hexamethyldisilazane (HMDS: (CH₃)₃-Si-NH-Si-(CH₃)₃) based treatment performed on a porous ULK material. The treatment reveals a beneficial effect on the sidewalls restoration as well as a gain in the IMD electrical performances after integration.     

Development of a permittivity extraction method for ultra low k dielectrics integrated in advanced interconnects

An extraction method to determine the permittivity of ultra low k (ULK) dielectrics on real integrated structures is presented. It is a two-step method based on a comparison between measured and simulated capacitance. A best-estimate value of the k_ULK value is first extracted with optimization software coupled to capacitance extraction software. Secondly, uncertainties on material and process parameters are considered to determine an error margin on the best-estimate extracted k value. The uncertainty on the best-estimate value is approximated by a function of the uncertainties on material and process variables. This function is calculated using a multi-linear approximation model and a numerical design of experiments. The same method is applied for the extraction of a ULK material k value (k_ULK) value and an effective k value (k_eff) but with two different simulation structures. In the simulation structure used for k_eff extraction, an equivalent dielectric layer including the ULK layer, the etch-stop and capping layers is used. This method was applied to metal 1 single damascene structures. First results of extraction are presented for two different ULK dielectrics. With the estimated uncertainty used for the parameters in this work, the uncertainties obtained for the best-estimate value of k_ULK and k_effective are significant. Due to the linearity of the model, the method is still applicable with different values for parameters uncertainty. An analysis work will be realized to improve the parameters uncertainty estimation. Future work will also include extraction of ULK permittivity for more complex structures like double damascene structures.     

Surface properties restoration and passivation of high porosity ultra low-k dielectric (k ∼ 2.3) after direct-CMP

Surface hydrophilisation and effective k-value degradation have been reported in literature after direct-CMP of high porosity SiOC films (without a protective capping layer). In the sequel, attempts to restore ultra low-k (ULK) material initial properties after a standard CMP and post-CMP cleaning process are reported. Annealing treatment has shown to be valuable to remove residual organics and water absorbed at the ultra low-k material surface after direct-CMP. However, as the hydrophilicity of the polished surface remains unchanged, it does not prevent moisture uptake, leading to an increase in k-value with time. Therefore, in order to restore hydrophobic properties and to stabilize the surface in time, three silylating agents - containing chlorosilane reactive groups (-SiMe_nCl_3−n) as well as hydrophobic methyl functions (-CH₃) in their structure - have been employed in liquid, gas or dense CO₂ phases on the CMP-induced damaged ULK layers. While each of these organic treatments is efficient to restore hydrophobicity on post-CMP ULK surfaces, only one of them proved to be able to keep the k-value low (comparable to the ULK pristine k-value) and stable in time, without inducing significant change in porosity of the ULK material.     

Investigation of physical and chemical property changes of ultra low-κ SiOCH in aspect of cleaning and chemical repair processes

The physical and chemical property changes of chemical vapor deposited ultra low-κ (ULK) SiOCH dielectric films due to different post ash treatments were studied by Auger electron spectroscopy, ellipsometric porosimetry and surface free energy evaluation. Structural changes in the ULK layer with respect to the carbon content were analyzed. Using a downstream and a reactive ion etch process for photo resist removal a reduction of carbon was observed. For different plasma gas chemistries the pore size reduction depends first on the process condition (downstream or reactive ion etch) and then on the gas. Differences in the pore size then also influence the amount of carbon depletion besides the influence of the gases used for photo resist processes. The damage at the surfaces was characterized by contact angle measurements providing both the polar and dispersive part of the surface free energy. The wettability of different solvents and repair chemicals was classified calculating their surface free energies and comparing those energies with the surface free energies of modified ULK surface. It is shown that especially reducing gases provide a surface free energy with a higher dispersive part compared to oxidative plasma treatments. Furthermore it was found that the wettability of repair chemicals and solvents strongly changes for reductive based strip processes with plasma exposure time, since a high variation of the surface free energy occur.     

多孔硅有效介电函数研究

采用改进过的Maxwell-Garnett模型研究了入射光波长和多孔硅的孔隙率对反射光谱和介电光谱的影响,结果表明:(1)随着入射光波长的增大,多孔硅的反射率先增大后减小,而随着孔隙率的增大反射光谱出现了明显的下塌趋势,且孔隙率越大下塌得越明显;(2)随着孔隙率的增加,多孔硅复介电光谱出现明显的蓝移现象,且多孔硅有效介电常数的实部和虚部均变小.此外还对这种现象给出了较为合理的解释.     

低压ZnO压敏陶瓷晶界特性的研究

借助 HP4192 A低频阻抗分析仪 ,分析了低压 Zn O压敏陶瓷的 C- V特性及介电和损耗特性、添加物对Zn O压敏瓷晶界电学特性的影响。探讨了热处理气氛对 Zn O晶粒边界电性能的作用机理。实验结果表明 :Na+ 掺杂量增加时 ,施主浓度基本保持不变 ,而势垒高度、界面态密度和耗尽层宽度增加 ;在空气中退火 ,样品的施主浓度减少 ,势垒高度降低 ;在 Ar气中退火样品的施主浓度基本保持不变 ,而势垒高度下降较大 ;在音频范围内 ,Zn O压敏瓷具有很高的介电常数 (εr约 130 0 ) ;在 10 5～ 10 6 Hz范围内 ,εr下降较明显 ,与此对应 ,介质损耗角正切 tgδ在 10 5～ 10 6 Hz范围内出现一个峰值 ,该峰具有扩展的德拜驰豫峰特征     

Inorganic–Organic Hybrid Dielectrics for Energy Conversion: Mechanism,Strategy, and Applications

Dielectric materials with higher energy storage and electromagnetic (EM) energy conversion are in high demand to advance electronic devices, military stealth, and mitigate EM wave pollution. Existing dielectric materials for high-energy-storage electronics and dielectric loss electromagnetic wave absorbers are studied toward realizing these goals, each aligned with the current global grand challenges. Libraries of dielectric materials with desirable permittivity, dielectric loss, and/or dielectric breakdown strength potentially meeting the device requirements are reviewed here. Regardless, aimed at translating these into energy storage devices, the oft-encountered shortcomings can be caused by either of two confluences: a) low permittivity, high dielectric loss, and low breakdown strength; b) low permittivity, low dielectric loss, and process complexity. Contextualizing these aspects and the overarching objectives of enabling high-efficiency energy storage and EM energy conversion, recent advances in by-design inorganic–organic hybrid materials are reviewed here, with a focus on design approaches, preparation methods, and characterization techniques. In light of their strengths and weaknesses, potential strategies to foster their commercial adoption are critically interrogated.     

Analysis of thermal stresses in copper interconnect/low-k dielectric structures

Numerical simulations of thermal stresses in copper (Cu) interconnect and low-k dielectric systems are carried out. The three-dimensional (3-D) finite-element analysis assumes a two-level metal structure connected by a via. Mechanical deformation is generated by thermal expansion mismatches during cooling and cyclic temperature changes. The thin barrier/etch stop layers, as well as oxide or polymer-based low-k dielectric materials, are all taken into account in the model. The stress and deformation fields are examined in detail; salient features having direct implications in device reliability are illustrated with representative contour plots. It is found that the use of low-k material in place of traditional oxide dielectric significantly reduces the triaxial tensile stresses in Cu but enhances plastic deformation, especially in the via region. The compliant low-k material causes the thin barrier layers to bear very high stresses. Deformation in the Cu line and via structure is more affected by the thermal expansion property of the dielectric, but the stresses in the barrier layers are more influenced by the elastic modulus of the dielectric.     

Reliability challenges for copper low-k dielectrics and copper diffusion barriers

The performance of interconnects containing micro- (pore size smaller than 2 nm) and meso-porous (pore size larger than 2 nm) interlevel dielectrics is influenced by material selection, integration scheme and virtually all fabrication steps. It is generally reported that the reliability margin of the dielectric/barrier/copper system is shrinking. Barrier and dielectric integrity play a most important role in line-to-line leakage and Time Dependent Dielectric Breakdown (TDDB) reliability. TDDB has never been an issue for Cu-SiO₂ interconnects, but for sub-100 nm copper/barrier/low-k systems it becomes challenging. When monitoring the integrated dielectric properties early failures can be caused by weak integration interfaces, dielectric damage during the integration, defective diffusion barrier or other non-uniformities related to the damascene process. Recent advances are reviewed along with examples and reference to state of the art.     

低温烧结铁氧体粉料的最新进展

以国家“86 3”计划重大项目和第八届国际铁氧体会议重要论文为据 ,综合分析、论述了低温烧结铁氧体粉料的进展状况。重点介绍了固相反应法 Ni Cu Zn铁氧体、Mg Cu Zn铁氧体和六角晶系 Co2 Z铁氧体。同时报道了具有世界领先水平的软化学法 Ni Cu Zn铁氧体和六角晶系 Co2 Z铁氧体成果     

Investigation on interracial and electrical properties of Ge MOS capacitor with different NH3-plasma treatment procedure

The effects of different NH3-plasma treatment procedures on interracial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HfTiON/TaON were investigated.The NH3-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric,i.e.before or after interlayer (TaON)deposition,or after deposition ofhigh-k dielectric (HfTiON).It was found that the excellent interface quality with an interface-state density of 4.79 × 1011 eV-1cm-2 and low gate leakage current (3.43 × 10-5 A/cm2 at Vg =1 V) could be achieved for the sample with NH3-plasma treatment directly on the Ge surface before TaON deposition.The involved mechanisms are attributed to the fact that the NH3-plasma can directly react with the Ge surface to form more Ge-N bonds,i.e.more GeOxNy,which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeOx interfacial layer,and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH3-plasma.     

Porosity and structure evolution of a SiOCH low k material during post-etch cleaning process

In the back end of line (BEOL) interconnections for 65 nm and beyond technology nodes, the integration of porous dielectric materials is now needed to improve signal propagation. In order to develop and optimize etching and cleaning process steps that may degrade the dielectric material, the characterization of ultra-low k porosity becomes mandatory. In this paper, the impact of wet cleaning with diluted HF solution was characterized depending on several plasma treatments. In particular, we focused on pore sealing effects after plasma and its persistency after wet treatments. It was demonstrated that methyl silsesquioxane (MSQ) thin film dissolution in diluted HF is not linear with process time, meaning that the material is not homogeneous. Depending on the plasma treatment, the thin layer created on the top surface is porous and does not protect the material from chemical dissolution. On contrary, some plasma treatment creates a thin layer with a very low permeability (sealed porosity) that acts as a protective coating against dissolution in diluted HF. Moreover, its porosity remains sealed, and pore sealing effect is not impacted by this cleaning process.     

Comparison of TiO2 and other dielectric coatings for buried‐contact solar cells: a review

This paper compares the optical, electronic, physical and chemical properties of dielectric thin films that are commonly used to enhance the performance of bulk silicon photovoltaic devices. The standard buried‐contact (BC) solar cell presents a particularly challenging set of criteria, requiring the dielectric film to act as: (i) an anti‐reflection (AR) coating; (ii) a film compatible with surface passivation; (iii) a mask for an electroless metal plating step; (iv) a diffusion barrier for achieving a selective emitter; (v) a film with excellent chemical resistance; (vi) a stable layer during high‐temperature processing. The dielectric coatings reviewed here include thermally grown silicon dioxide (SiO₂), silicon nitride deposited by plasma‐enhanced chemical vapour deposition (a‐ SiN_x :H) and low‐pressure chemical vapour deposition (Si₃N₄), silicon oxynitride (SiON), cerium dioxide (CeO₂), zinc sulphide (ZnS), and titanium dioxide (TiO₂). While TiO₂ dielectric coatings exhibit the best optical performance and a simple post‐deposition surface passivation sequence has been developed, they require an additional sacrificial diffusion barrier to survive the heavy groove diffusion step. A‐ SiN_x :H affords passivation through its high fixed positive charge density and large hydrogen concentration; however, it is difficult to retain these electronic benefits during lengthy high‐temperature processing. Therefore, for the BC solar cell, Si₃N₄ films would appear to be the best choice of dielectric films common in industrial use. Copyright © 2004 John Wiley & Sons, Ltd.