Voltage dependent photocurrent collection in CdTe/CdS solar cells

The voltage dependence of the photocurrent J_L(V) of CdTe/CdS solar cells has been characterized by separating the forward current from the photocurrent at several illumination intensities. J_L(V) reduces the fill factor (FF) of typical cells by 10–15 points, the open circuit voltage (V_OC) by 20–50 mV, and the efficiency by 2–4 points. Eliminating the effect of J_L(V) establishes superposition between light and dark J(V) curves for some cells. Two models for voltage dependent collection give reasonable fits to the data: (1) a single carrier Hecht model developed for drift collection in p‐i‐n solar cells in which fitting yields a parameter consistent with lifetimes of 10⁻⁹ s as measured by others; or (2) the standard depletion region and bulk diffusion length model fits almost as well. The simple Hecht‐like drift collection model for photocurrent gives very good agreement to J(V) curves measured under AM1·5 light on CdTe/CdS solar cells with FF from 53% to 70%, CdTe thickness from 1·8 to 7·0 µm, in initial and stressed states. Accelerated thermal and bias stressing increases J_L(V) losses as does insufficient Cu. This method provides a new metric for tracking device performance, characterizes transport in the high field depletion region, and quantifies a significant FF loss in CdTe solar cells. Copyright © 2007 John Wiley & Sons, Ltd.     

Effect of the design and technology factors on electrical characteristics of the Au/Ti-n-GaAs Schottky diodes

Electrical properties of the Au/Ti-n-GaAs Schottky diodes are studied in relation to the production technology. The forward and reverse current-voltage characteristics of the diodes at low electric fields are analyzed on the basis of the mechanism of thermionic emission through the metal-semiconductor barrier. It is assumed that an increase in the reverse currents in the voltage range from 20 to 60 V can be accounted for by the Pool-Frenkel effect. The excess reverse currents at voltages higher than 60 V are caused by the phonon-assisted tunneling via deep states in the depletion region of the semiconductor.     

强电场对NiO电子结构性质的影响研究

基于平面波密度泛函理论研究了电场强度为10V?nm-1下立方结构氧化镍的电子结构性质。结果表明:立方相氧化镍在电场强度10V?nm-1下呈现导体的能带结构,价带上移到导带,态密度谱图在多个能量取得最值,局域化效应增强,费米能级附近的态密度增大为原系统的2倍多。费米能级上的载流子浓度由4 e/eV增大到15 e/eV,这源于Op、Nis、Nid态对费米面的贡献。强电场下的电子在不同量子状态之间显示了明显的转移,介电函数计算表明强电场下体系在0.32 eV附近具有最大的吸收,吸收峰峰值66.89。强电场明显调控了NiO的电学、光学和场致光吸收性能。     

New technique for measuring the threshold voltage in MOS devices

The present paper describes an experimental method that can be used to measure the threshold voltage in MOS devices in the form of transistors or capacitors. The proposed method is based on the detection of the non-steady-state/steady-state transition of the surface potential at the oxide–semiconductor interface of a MOS device, when it is swept from depletion to inversion regions. This detection is carried out as follows: a set of current versus gate signal frequency measurements, for different voltage amplitudes, is performed. The frequency values corresponding to the maximum measured current (optimum frequency) f_m, are read. Several gate voltage versus optimum frequencies (f_m–V_G) curves are plotted for gate voltage values ranging from 0.2 to 3 V with a 0.1 V step increment. The (f_m–V_G) curves are found to undergo an abrupt change of slope at a specific gate voltage value. The value of threshold voltage is extracted from the critical points of the former curves. Experiments have been carried out on different devices. The measured values of threshold voltage are found to be in good agreement to those obtained by the conventional I_D–V_GS and simulation methods as well as that supplied by the device manufacturer.     

Influence of an impurity profile on the determination of interface states

In order to determine the density of interface states from C(V) curves for high test frequencies, a comparison is made with a computed curve for uniform impurity concentration but identical minimum capacitance. The curves calculated for a doping profile (due, say, to acceptor depletion near the surface of a p-type semiconductor) are assumed to represent the measured C(V) curves of MOS diodes. A number of “charges in interface states” (8 × 10¹⁰ cm^?2 in the given example) are simulated by the impurity profile. This shows that it is not sufficient to introduce a mean effective substrate impurity concentration by adapting the minimum capacitance in the inversion region.The same accordingly applies for the C(V) curves for low test frequencies. The error due to “simulated interface states” is reduced somewhat, but it remains the altered relation between the applied voltage and the surface potential.     

Carrier transport and memory mechanisms of multilevel resistive memory devices with an intermediate state based on double-stacked organic/inorganic nanocomposites

Multilevel resistive memory devices with an intermediate state were fabricated utilizing a poly(methylmethacrylate) (PMMA) layer sandwiched between double-stacked PMMA layers containing CdSe/ZnS core–shell quantum dots (QDs). The current–voltage (I–V) curves on a Al/[PMMA:CdSe/ZnS QD]/PMMA/[PMMA:CdSe/ZnS QD]/indium-tin-oxide/glass device at low applied voltages showed current bistabilities with three states, indicative of multilevel characteristics. A reliable intermediate state was realized under positive and negative applied voltages. The carrier transport and the memory mechanisms of the devices were described on the basis of the I–V curves and energy band diagrams, respectively. The write-read-erase-read-erase-read sequence of the devices showed rewritable, nonvolatile, multilevel, and memory behaviors. The currents as functions of the retention time showed that three current states were maintained for retention times larger than 1 × 10⁴ s, indicative of the good stability of the devices.     

Effects of a buffer layer on free-carrier depletion in n-type GaAs

The authors develop a simple model for the effects of a buffer layer on free-carrier depletion from a conductive semiconductor layer. Poisson's equation is solved in the depletion approximation to give an expression for the sheet free-carrier charge transferred from a conductive semiconductor layer to acceptor (or donor) states at interfaces or in the bulk material. The principal goal is to show that a relatively thin, undoped buffer layer between the substrate and active layer can dramatically lower the free-carrier loss to substrate interface states. Data on molecular-beam epitaxial, n-type GaAs agrees well with the theory, but show that there still is some loss at the interface between the active layer and buffer layer     

Schottky-barrier source/drain MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate

This letter presents a simple low-temperature process to fabricate Schottky-barrier (SB) MOSFETs that integrates a midgap metallic gate (tungsten). The device architecture is based on a thin (10 nm) and lowly doped silicon-on-insulator film that provides a threshold voltage of -0.3 V independent on the depletion charge and therefore not sensitive to variations in film thickness and doping. A gate encapsulation technique using an SiO/sub 2/-like hydrogen silsesquioxane capping layer features 15-nm-wide spacers and ensures the compatibility with the PtSi self-aligned silicide process. Long-channel devices present an ideal subthreshold swing of 60 mV/dec, over six decades of I/sub on//I/sub off/ without any sign of sublinear upward bending of the I/sub DS/--V/sub DS/ curves at low drain voltage.     

RF Sputtered gold-amorphous silicon Schottky-barrier diodes

Gold Schottky-barrier diodes formed on reactively sputtered amorphous silicon thin films have been investigated. Device forwardI-Vcharacteristics are well modeled as a Schottky diode in series with a temperature activated series resistor. At 300K, the forward current indicates a diode correction factor of 1.4 and a saturation current of 5.8 × 10^-10A/cm². The metal-semiconductor barrier height is 0.93 eV. Capacitance versus frequency measurements indicate a depletion region thickness of 3000 Å. In the depletion region, the mobility-lifetime products are estimated to be of the order of 5 × 10^-11cm²/V which is substantially less than the value of 10^-7cm²/V in the quasi-neutral region, It is suggested that deep gap states are responsible for this difference. Carrier recombination in the depletion region limits the photovoltaic performance.     

C/V measurements of m.i.s. structures on n-InSb formed by room temperature reactive deposition of Si3N4

C/V measurements were performed on Si3N4 layers on n-InSb substrates, which had been grown in an r.f. glow discharge at room temperature. Surface state densities on B-type (111) substrates were substantially larger than on A-type substrates. These structures could be biased to accumulation, to depletion, and even to inversion.     

A GaAs MOSFET with a liquid phase oxidized gate

Low leakage current density (as low as 10^-8 A/cm² at an applied voltage of 5 V) and high breakdown electrical field (larger than 4.5 MV/cm) of the liquid phase chemical-enhanced oxidized GaAs insulating layer enable application to the GaAs MOSFET. The oxide layer is found to be a composite of Ga₂O₃, As, and As₂O₃. The n-channel depletion mode GaAs MOSFET's are demonstrated and the I-V curves with complete pinch-off and saturation characteristics can be seen. A transconductance larger than 30 mS/mm can be achieved which is even better than that of MESFET's fabricated on the same wafer structure     

Silicon npn bipolar transistors with indium-implanted base regions

In this paper, silicon npn bipolar transistors with indium-implanted base regions are discussed. Polysilicon emitter bipolar transistors are fabricated using a standard 0.5-μm BIC-MOS process flow where the base BF₂ implant is replaced by an indium implant. In indium-implanted transistors, the integrated hole concentration (G_b) in the quasi-neutral base is reduced due to incomplete ionization of indium acceptor states. The novel utilization of this impurity freeze-out effect results in much increased collector currents and common-emitter transistor gains (h_fe) compared to boron-implanted transistors. Also, since indium acceptor states in depletion regions become fully ionized, the spreading of the reverse-biased collector-base junction depletion region into the transistor base (base-width modulation) is minimized. Hence, for indium base bipolar transistor an improved h_fe-V_A product is anticipated. Our first attempt at fabricating bipolar transistors with indium-implanted base regions resulted in devices with greatly increased collector current, impressive gains of h_fe≈1600, excellent collector current saturation characteristics, an Early Voltage of V_A≈10 V, h_fe-V_A product of 16000 (implying an extended device design space), base-emitter breakdown voltages of BV_EBO≈9.6 V, and a cut-off frequency of f_t=17.8 GHz     

Large-area low-capacitance InP/InGaAs MSM photodetectors forhigh-speed operation under front and rear illumination

Large-area long-wavelength metal-semiconductor-metal (MSM) photodetectors fabricated on the Fe-doped InP/InGaAs material system have been characterised under front and rear illumination employing different thicknesses of the photoactive layer. With a 350 μm diameter detection area, theoretically limited capacitance values (0.75 pF) and very low depletion voltages (<1 V) were obtained. For an active layer thickness of 0.7 μm, the devices show an external quantum yield of up to 60% and a bandwidth of 0.95 GHz at 10 V bias     

Rectification at n-n GaAs:(Ga,Al)As heterojunctions

n-n Ga0.7Al0.3As: GaAs heterojunction structures have been grown by l.p.e., with 1 × 1015 cm-3 net carriers in the ternary. N/W profiling across the heterojunction shows an accumulation region on the GaAs side and a depletion region on the (Ga, Al)As side. I/V characteristics at room temperature show significant rectification.     

Annealing of Si---SiO2 interface states using Ar-ion-implant-damage-gettering

The effectiveness of Ar-ion-implant damage gettering on the Si---SiO₂ interface states has been investigated using MOS techniques and Rutherford backscattering. Silicon wafers of (100) orientation were used in the study. Some wafers were intentionally contaminated with Au and then Ar-ion-implant was performed on the back surface and the damaged layer subsequently annealed at 1050°C for times of 15 and 60 min in a nitrogen ambient. The quasi-static I–V technique of Kuhn was used to obtain experimental curves which were correlated with the theory to extract the interface state density and distribution. The effectiveness of Ar-ion-implant in removing Au from the interface is clearly demonstrated by the structure of the quasi-static I–V curves. Rutherford backscattering of ¹⁴N⁺ ions was carried out on the wafers indicating that the removal of gold from the interfacial traps is associated with its removal from the bulk.     

不同栅压应力下1.8V pMOS热载流子退化机理研究

本文详细研究了不同栅压应力下1.8V pMOS器件的热载流子退化机理.研究结果表明,随着栅压应力增加,电子注入机制逐渐转化为空穴注入机制,使得pMOS漏极饱和电流(I_dsat)、漏极线性电流(I_dlin)及阈值电压(V_th)等性能参数退化量逐渐增加,但在V_gs=90%*V_ds时,因为没有载流子注入栅氧层,使得退化趋势出现转折.此外,研究还发现,界面态位于耗尽区时对空穴迁移率的影响小于其位于非耗尽区时的影响,致使正向I_dsat退化小于反向I_dsat退化,然而,正反向I_dlin退化却相同,这是因为I_dlin状态下器件整个沟道区均处于非耗尽状态.     

Effect of leaky SAW parameters on V(z) curves obtained by acoustic microscopy

V(z) curves are measured by a reflection-acoustic-microscope system in the nonscanning version. As for V(z) curves, leaky SAWs at the interface of water/solid are known to play an important role. In the letter, the effect of leaky SAW parameters, i.e. phase velocity and attenuation factor, has been numerically analysed on V(z) curves. The numerical calculation is performed for an acoustic line-focus-beam lens by introducing an idealised reflectance function where only a solution of leaky SAW is taken into consideration. It is clarified that the interval of dips and the shape of V(z) curves are strongly affected by the phase velocity and the attenuation factor, respectively.     

Hot-carrier effects in Hydrogen-passivated p-channel polycrystalline-Si MOSFET's

The dependence of hot-carrier effects on channel length and stress-bias voltage in hydrogen-passivated accumulation-mode p-channel polycrystalline-Si MOSFET's operating in the saturation region has been studied, Before stress, these devices exhibit a minimum value of current at VGS≈ 0 V but as VGSincreases above 0 V, they show an increase in (leakage) current due to field-enhanced generation of carriers near the drain. After stress, the current at VGS≈ 0 V increases slightly with respect to its pre-stress value. However, the current then monotonically decreases as VGSincreases above 0 V unlike the situation before stress. No change in reverse mode (source and drain reversed) characteristics and no change in the ON-state (VGS< 0 V) forward-mode characteristic was observed after stress. These observations are shown to be due to hot-carrier-induced acceptor-type interface states near the drain in forward-mode operation.     

层状结构铁电薄膜中频率对界面电位降的影响

利用准分子激光原位沉积方法制备了层状结构铁电薄膜,借助HP4192A低频率阻抗分析仪对样品的C－V特性进行了测试,对同一频率下不同结构的铁电薄膜的界面电压降及不同频率下同一结构的铁电薄膜的界面电压降进行计算。结果表明,在同一频率下不同结构的铁电薄膜其界面电压降不同,同一结构的多层铁电薄膜在不同频度下其界面电压降也不同。不同的耗尽层厚度导致了界面电压降的不同。     

Planar integration of E/D-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment

A planar-fabrication technology for integrating enhancement/depletion (E/D)-mode AlGaN/GaN high-electron mobility transistors (HEMTs) has been developed. The technology relies heavily on CF/sub 4/ plasma treatment, which is used in two separate steps to achieve two objectives: 1) active device isolation and 2) threshold-voltage control for the enhancement-mode HEMT formation. Using the planar process, depletion- and enhancement-mode AlGaN/GaN HEMTs are integrated on the same chip, and a direct-coupled FET logic inverter is demonstrated. Compared with the devices fabricated by a standard mesa-etching technique, the HEMTs by a planar process have comparable dc and RF characteristics with no obvious difference in the device isolation. The device isolation by a plasma treatment remains the same after 400 /spl deg/C annealing, indicating a good thermal stability. At a supply voltage (V/sub DD/) of 3.3 V, the E/D-mode inverters show an output swing of 2.85 V, with the logic-low and logic-high noise margins at 0.34 and 1.47 V, respectively.