Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

A proposed magnetically enhanced reactive ion etcher for ULSI

An ultraclean (UC) magnetically enhanced reactive ion etcher (MERIE) is proposed to overcome the limitations of the present-state MERIE available commercially. The sensitivity of gas compositions, pumping speed, substrate temperature and magnetic field intensity are discussed as examples of hardware-related process limitations. Five major configuration changes are proposed in the system: (1) improved effective pumping speed; (2) supplementary magnets for uniform and stable plasma distribution; (3) dual RF excitation for independent control of ion energy and flux; (4) DC-biased shield electrode for minimum chamber material contamination; and (5) DC-biased substrate. A study with a dual RF excitation system found that DC-baising the Si substrate in low-energy SiO₂ etching process can significantly reduce the Si etching rate by impeding positive ions from reaching the substrate. In addition, SiO₂ to Si etching rate selectivity can be significantly improved during the overetch step in SiO₂ etching of high-aspect-ratio contact holes     

InAs/GaSb Ⅱ类超晶格长波焦平面阵列台面ICP刻蚀技术研究

本文采用SiO₂/SiN作为掩膜对InAs/GaSbⅡ类超晶格红外材料进行感应耦合等离子体（ICP）刻蚀条件研究,得到InAs/GaSbⅡ类超晶格较好的刻蚀条件以提升红外探测器性能。对ICP刻蚀过程中容易出现台面侧向钻蚀以及台面底部钻蚀两种现象进行了详细研究,通过增加SiO₂膜层厚度以及减小Ar气流量,可有效减少台面侧向钻蚀;通过减小下电极射频功率（RF）,可有效消除台面底部钻蚀。采用适当厚度的SiO₂/SiN掩膜以及优化后的ICP刻蚀参数可获得光亮平整的刻蚀表面,表面粗糙度达到0.193 nm;刻蚀台面角度大于80°,刻蚀选择比大于8.5:1;采用优化后的ICP刻蚀条件制备的长波640×512焦平面器件暗电流密度降低约1个数量级,达到3×10－4 A/cm2,响应非均匀性、信噪比以及有效像元率等相关指标均有所提高,并获得了清晰的焦平面成像图。     

Attenuation losses in electron cyclotron resonance plasma etched AlGaAs waveguides

AlGaAs/GaAs ridge waveguides with fundamental mode attenuation ≤ 1 dBcm⁻¹ at a wavelength of 1.32 μm and channel widths of 4–4.5 μm are realized by ECR (Electron Cyclotron Resonance) plasma etching in BCl₃/Cl₂/Ar/N₂ chemistries. The choice of both plasma chemistry and initial mask scheme (single layer photoresist or trilevel resist) has a significant effect on the attenuation losses.     

Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

Study of etch rate characteristics of SF6/He plasmas byresponse-surface methodology: effects of interelectrode spacing

The characteristics of SF₆/He plasmas which are used to etch Si₃N₄ have been examined with experimental design and modeled empirically by response-surface methodology using a Lam Research Autoetch 480 single-wafer system. The effects of variations of process gas flow rate (20-380 sccm), reactor pressure (300-900 mtorr). RF power (50-450 W at 13.56 MHz), and interelectrode spacing (8-25 mm) on the etch rates of LPCVD (low-pressure chemical vapor deposition) Si₃N₄, thermal SiO₂, and photoresist were examined at 22±2°C. Whereas the etch rate of photoresist increases with interelectrode spacing between 8 and 19 mm and then declines between 19 and 25 mm, the etch rate of Si₃N ₄ increases smoothly from 8 to 25 mm, while the etch rate of thermal SiO₂ shows no dependence on spacing between 8 and 25 mm. The etch rates of all three films decrease with increasing reactor pressure. Contour plots of the response surfaces for etch rate and etch uniformity of Si₃N₄ as a function of spacing and flow rate at constant RF power (250 W) display complex behavior at fixed reactor pressures. A satisfactory balance of etch rate and etch uniformity for Si₃N₄ is predicted at low reactor pressure (~300 mtorr), large electrode spacing (12-25 mm), and moderate process gas flow rates (20-250 sccm)     

Fabrication of low dielectric constant materials for ULSImultilevel interconnection by plasma ion implantation

High dose-rate plasma ion implantation (PII) has been utilized to produce low dielectric constant (k) SiO₂ films for high quality interlayer dielectrics. The SiO₂ films are fluorine-doped/carbon-doped by PII with CF₄ plasma in an inductively-coupled plasma (ICP) reactor. It is found that the use of CF ₄ doping results in exceptional dielectric properties which differ significantly from fluorinated SiO₂. The dielectric constant of the SiO₂ film is reduced from 4.1 to 3.5 after 5 minute PII, other electrical parameters such as bulk resistivity and dielectric breakdown strength are also improved     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

Anisotropic etching characteristics of platinum electrode forferroelectric capacitor

The effect of etch parameters of platinum etching using Cl₂ /CO plasma on the etching properties and the etch profiles was investigated. The etching characteristics with respect to substrate temperature are different in two temperature regions below and above 210°C and significantly depended on Cl₂ concentration in each temperature region. The etch rates of Pt were enhanced suddenly at the substrate temperature of around 210°C when Cl₂ concentration is 50-80%. The etch rates of Pt below 210°C did not change much with increasing temperature. The selectivity of Pt over SiO ₂ was governed by the etch rate of SiO₂ in the lower temperature region but determined by the etch rates of Pt in the higher temperature region. The anisotropy of etch profiles was high enough to achieve vertical pattern without etch residues in the lower temperature region for the application in fabricating 1-Gbit era. In the higher temperature region, however, the slopes of etch profiles due to the volatile products of Pt were found. XPS was used to analyze the surface atomic compositions after various etching treatments     

A stacked capacitor technology with ECR plasma MOCVD(Ba,Sr)TiO3 and RuO2/Ru/TiN/TiSixstorage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO₃ thin films is described, The four-layer RuO₂/Ru/TiN/TiSi_x, storage node configuration allows 500°C processing and fine-patterning down to the 0.20 μm size by electron beam lithography and reactive ion etching. Good insulating (Ba_0.4Sr_0.6)TiO₃ (BST) films with an SiO₂ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1×10^{-/6 A}cm² at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 μm size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 μm² with only the 0.3 μm high-storage electrodes     

High performance poly-crystalline silicon thin film transistorsfabricated using remote plasma chemical vapor deposition of SiO2

A remote plasma chemical vapor deposition (RPCVD) of SiO₂ was investigated for forming an interface of SiO₂/Si at a low temperature below 300°C. A good SiO₂/Si interface was formed on Si substrates through decomposition and reaction of SiH₄ gas with oxygen radical by confining plasma using mesh plates. The density of interface traps (D_it) was as low as 3.4×10¹⁰ cm^-2eV^-1. N- and p-channel Al-gate poly-Si TFTs were fabricated at 270°C with SiO₂ films as a gate oxide formed by RPCVD and laser crystallized poly-crystalline films formed by a pulsed XeCl excimer laser. They showed good characteristics of a low threshold voltage of 1.5 V (n-channel) and -1.5 V (p-channel), and a high carrier mobility of 400 cm²/Vs     

A new method of forming a thin single-crystal silicon diaphragmusing merged epitaxial lateral overgrowth for sensor applications

Merged epitaxial lateral overgrowth (MELO) of silicon was combined with an SiO₂ etch stop to form a 9-μm-thick and 250-μm×1000-μm single-crystal Si membrane for micromechanical sensors. When epitaxial lateral overgrowth (ELO) silicon merges on SiO₂ islands, it forms a local silicon-on-insulator (SOI) film of moderate doping concentration. The SiO₂ island then acts as a near-perfect etch top in a KOH- or ethylenediamine-based solution. The silicon diaphragm thickness over a 3-in wafer has a standard deviation of 0.5 μm and is precisely controlled by the epitaxial silicon growth rate (≈0.1 μm/min) rather than by conventional etching techniques. Diodes fabricated in the substrate and over MELO regions have nearly identical reverse-bias currents, indicating good quality silicon in the membrane     

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Low-damage hard-mask (HM) plasma-etching technology for porous SiOCH film (k=2.6) has been developed for robust 65-nm-node Cu dual damascene interconnects (DDIs). No damage is introduced by fluorocarbon plasma etching irrespective of whether rigid (k=2.9) or porous (k=2.6) SiOCH films are used, due to the protective CF-polymer layer deposited on the etched sidewall. The etching selectivity of the SiOCH films to the inorganic HMs is kept high by controlling the radical ratio of carbon relative to oxygen in the etching plasma gas. However, oxidation damage penetrates the films from the sidewalls due to the O₂ plasma used for photoresist ashing. This damage is increased by the porous structure. As a result, we developed a via-first multi-hard-mask process for the DD structure in porous SiOCH film with no exposure to O ₂-ashing plasma, and we controlled the via-taper angle by RF bias during etching. We fabricated robust Cu DDIs with tapered vias in porous SiOCH film that can be applied to 65-nm-node ULSIs and beyond     

The heterogenous integration of GaN thin-filmmetal-semiconductor-metal photodetectors onto silicon

The heterogeneous integration of GaN thin-film metal-semiconductor-metal (MSM) photodetectors onto a host substrate of SiO₂-Si is reported. Thin-film GaN photodetectors were separated from the lithium gallate (LiGaO₂) growth substrate using selective etching, and contact bonded onto a SiO₂-Si host substrate. The thin-film MSMs exhibited a dark current of 13.36 pA and an UV photoresponse at 308 nm of 0.11 A/W at a reverse bias voltage of 20 V. This first demonstration of GaN thin-film device integration onto SiO₂-Si using a low-temperature integration process, combined with the advances in GaN material quality on LiGaO₂ substrates, enables the integration of GaN devices with Si circuitry for heterogeneously integrated systems     

Transformer coupled plasma dielectric etch for 0.25 μm technologies

Manufacturable etch processes for 0.18 μm technology TEOS bi-level contacts and vias (TEOS or TEOS/FOX/TEOS) are demonstrated in a low pressure high density reactor. Good CD control and high yields are demonstrated for structures down to 0.25 μm. In the process regimes used, the photoresist etch rate and the selectivity to underlayer are correlated with the amount of free fluorine in the plasma. The same TCP 9100 reactor can be used for low k polymer (Silk™ from Dow Chemical) etching with in situ hardmask open. A compromise between hard mask facetting and bowing has to be made unless passivating gases are added to an O₂/N₂ chemistry. For several architectures, initial results show potential integration with Cu.     

High-performance vertical-power DMOSFETs with selectively silicidedgate and source regions

A power FET (field-effect transistor) structure with selectively silicided gate and source region is described. This structure simultaneously lowers the gate sheet-resistance and the source contact resistance. The gate-source isolation was provided by plasma etching conformally deposited chemical vapor deposition (CVD) oxide using a photoresist mask. This structure has resulted in an order of magnitude improvement in the gate sheet resistance and about 25% improvements in the device's on-resistance (the resistance when conducting in the on-state) compared to previously reported nonsilicided conventional power FETs. Extremely low-resistance Al-TiW-TiSi₂ metallurgy with in situ sputter etching of the silicide surface prior to TiW deposition contributed to the reduction in the on-state resistance. Vertical-power DMOSFETs (double-diffused MOSFET) fabricated using this technology have a specific on-resistance of 0.53 Ω cm² for devices capable of blocking 50 V in the off state     

Plasma enhanced in situ chamber cleaning evaluated byextracted-plasma-parameter analysis

We have demonstrated that high-efficiency in situ chamber cleaning with short gas residence time is possible for SiO₂ etching chambers by use of NF₃ plasma, and that the endpoint determination of the cleaning is possible by monitoring the optical emission intensities of CO or H. Nitrogen trifluoride (NF₃), which has a low N-F bond energy, can generate a plasma with a high density of ions and radicals featuring low kinetic energy. The cleaning efficiency of several halogenated-gas plasmas has been evaluated based on extracted-plasma-parameter analysis. In this analysis important plasma parameters, such as ion energy and ion flux density, can be extracted through a simple rf waveform measurement at the plasma excitation electrode. The accuracy of this technique has been confirmed with a newly developed rf plasma direct probing method and by ion current measurements     

ECCP干法刻蚀条件下的TFT基板绝缘层过孔腐蚀的改善

过孔搭接失效一直是TFT-LCD行业中重点改善的不良之一。为了解决该不良,本文分析了不同刻蚀模式(ICP和ECCP)对过孔形貌的影响,利用四因子法研究ECCP模式刻蚀参数(压力、偏置/源极射频功率及O_2/SF_6气体比例)对刻蚀速率和均一性的影响,并得出ECCP过孔改善的最佳刻蚀参数。结果表明:ECCP模式下,氮化硅刻蚀过程中物理轰击对GI截面的下沿与Cu接触区域形成损伤后产生的缺陷,是诱发过孔腐蚀的主要因素,ICP模式无腐蚀。反应腔压力增大刻蚀速率增大,均一性下降;偏置射频功率增大,速率增大,均一性提高;源极射频功率增大,速率变化小,均一性下降;O_2/SF_6气体比例对速率影响小,O_2含量越高,均一性越高。为达到PR胶保护GI下沿截面的目的,反应压力增大到1.7Pa,偏置射频功率减小到30kW,源极功率增加到30kW,O_2/SF_6气体保持比例1∶1后,增加了氮化硅的刻蚀量,减小PR胶的内缩量,避免物理溅射表面损伤;同时刻蚀速率达到750nm/s,均一性达到10%,腐蚀发生率为10%～0,使ECCP刻蚀模式对过孔的腐蚀影响得到有效解决。     

Thin-gate SiO2 films formed by in situ multiple rapidthermal processing

A reliable method of forming very thin SiO₂ films (<10 nm) has been developed by rapid thermal processing (RTP) in which in situ multiple RTP sequences have been employed. Sub-10-nm-thick SiO₂ films formed by single-step RTP oxidation (RTO) are superior to conventional furnace-grown SiO₂ on the SiO₂ /Si interface characteristics, dielectric strength, and time-dependent dielectric-breakdown (TDDB) characteristics. It has been confirmed that the reliability of SiO₂ film can be improved by pre-oxidation RTP cleaning (RTC) operated at 700-900°C for 20-60 s in a 1%HCl/Ar or H₂ ambient. The authors discuss the dielectric reliability of the SiO₂ films formed by single-step RTO in comparison with conventional furnace-grown SiO₂ films. The effects and optimum conditions of RTC prior to RTO on the TDDB characteristics are demonstrated. The dielectric properties of nitrided SiO₂ films formed via the N₂O-oxynitridation process are described     

Ion milling properties of laterally emitting thin-filmelectroluminescent materials

A study has been undertaken of the ion milling properties of ZnS:Mn, Y₂O₃, Si₃N₄, SiO₂, SiO_xN_y, and Al versus the etching time, the acceleration voltage, and the angle of incidence of the ion beam. Different ZnS:Mn etched profiles have been fabricated by modifying the angle of incidence; these are in agreement with the reported simulations