Mass characterisation of organic transistors and Monte-Carlo circuit simulation

We present a method for designing organic circuits using Monte-Carlo based circuit simulation. The organic devices suffer from mismatch and variations that are due to systematic and random fluctuations in the process and material characteristics. In this work, we have used the variable range hopping model to extract the model parameters using a mass characterisation technique. The parameter fluctuations of organic transistors are taken into account and process corners determined based on static (noise margin) and transient (delay) characteristics. Thus a methodology is developed to find the parameter range of individual devices, within which the circuits are having good performance, for instance inverters working with desired noise margin. We also found out the critical parameters of the transistor, that predominantly affects the static and transient performance of an inverter. These critical parameters can be provided as input to the process engineers to fine tune the process. This information can also be used in developing robust circuit design techniques, which can overcome the variation effects of these critical parameters. Thus, a mass characterisation of transistors combined with the proposed method, allows robust circuit design in the presence of huge process variations.     

Robust Analog Design for Automotive Applications by Design Centering With Safe Operating Areas

The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or voltage stress, causes a shift of device parameters, for example threshold voltage $V_{rm th}$, which can also be modeled as a degradation of transistor parameters. Therefore, in order to design circuits, which are robust and reliable, analysis and optimization of their sensitivity to variations in model parameters is important. Furthermore, constraints on the operating regions and voltage differences of transistors are used in order to keep operating points stable over a large temperature range. In this work, using two circuits for automotive applications and current process development kits (PDK), we show how design centering software can be used to consider both sensitivity reduction towards model parameter variation and constraints to control safe operating areas (SOA). Beyond that a comparison of the constraint matrix method with two established methods of SOA checking is done.      

Variation

Variation afflicts the design, manufacture, and operation of integrated circuits. Techniques and tools are needed in three areas to address variation: statistical metrology, advanced process control, and design for manufacturability. First, statistical metrology seeks to characterize and model variations and their sources. Advanced metrology helps to understand geometric and material property variations, while variation test structures and test circuits enable study of the impact of specific or aggregate variations on performance. Second, advanced process control attempts to reduce process variation through sensing and feedback/feedforward control during fabrication. Third, design for manufacturability (DFM) seeks methods to improve performance and yield given process and environmental variation, through robust design, increased regularity, and other approaches. Finally, linkages between these areas, particularly between statistical metrology and DFM, will be important and empowering.     

Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 /spl mu/m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element selection and precise measurement are achieved with low parasitic resistance measurement buses and leakage-controlled switching circuits, which allow the measurement accuracy for a transistor, resistor, or capacitor of 90 pA, 11 m/spl Omega/, and 23 aF, respectively, in the 3/spl sigma/ range. The ability to obtain 29 008 samples from a chip enables statistical analysis of the variation in 148 elements of each chip with 240-/spl mu/m spatial resolution. This high resolution and large sample number allows us to precisely decompose the data into systematic and random variation parts with newly developed fourth-order polynomial fitting. Our methodology has been verified using a test chip fabricated by a 130-nm CMOS process with a 100-nm physical gate length and five Cu interconnect layers. In MOSFETs, the random part was dominant and indicated a certain /spl sigma/ value in every chip. In the case of the interconnect layers, the random and systematic parts of the resistance and the capacitance indicated variance fluctuations. By chip, by item, by size, by structure, random or systematic, the /spl sigma/ values of each variation show inconsistency which we believe is attributable to the Cu process. The correlation coefficients of systematic part between device element and ring oscillator frequency shown very high value (0.87-0.98), and those of a random part were low enough (-0.10-0.22) to prove the accuracy of decomposition.     

Average power analysis of sequential circuits using an autoregressive model

We present a new statistical technique for average power estimation in sequential circuits. Because of the feedback loops, power dissipations of sequential circuits in consecutive clock cycles are temporally correlated. The existence of data correlation makes it unsuitable to apply conventional techniques to average power inference, because the sample variance is no longer a maximum likelihood estimator. The convergence criterion derived from the biased variance estimation will be overly optimistic, causing power simulation to stop prematurely at a lower-than-specified estimation accuracy. To overcome this problem, we propose a systematic approach for modeling the power dissipation behavior of sequential circuits as an autoregressive random process. An accurate process variance can be obtained by the model parameters, which enables the derivation of a robust confidence interval of the average power. The interval is checked for convergence against a user-specified accuracy criterion. An iterative procedure is developed to invoke these steps repeatedly until the convergence specification is met. For a set of benchmark sequential circuits, this technique yields high accuracy and efficiency.     

Modeling of Variation in Submicrometer CMOS ULSI Technologies

The scaling of semiconductor technologies from 90- to 45-nm nodes highlights the need for accurate and predictive compact models that address the regime where small-scale physical effects become dominant. These demanding requirements on compact models extend beyond the core model to a suite of design tools that include extraction tools and statistical methods to account for unpredictable variation (e.g., random dopant fluctuations and polysilicon linewidth variation) and predictable variation (e.g., transistor response differences that are layout dependent). Layout-dependent or local environment differences are driven by factors such as lithography and novel performance-enhancing process techniques such as dual-stress nitride liner films. Sources of variation such as rapid thermal annealing temperature, low-frequency noise, and modeling of back-end-of-line elements need to be considered. The modeling of intradie and interdie variations, updated for small geometries, should be properly positioned in the design flow. This paper presents the challenges and results of compact modeling at the 65-nm node and beyond.     

Lack of Spatial Correlation in MOSFET Threshold Voltage Variation and Implications for Voltage Scaling

Due to increased variation in modern process technology nodes, the spatial correlation of variation is a key issue for both modeling and design. We have created a large array test-structure to analyze the magnitude of spatial correlation of threshold voltage $(V_{T})$ in a 180 nm CMOS process. The data from over 50 k measured devices per die indicates that there is no significant within-die spatial correlation in $V_{T}$. Furthermore, the across-chip variation patterns between different die also do not correlate. This indicates that Random Dopant Fluctuation (RDF) is the primary mechanism responsible for $V_{T}$ variation and that relatively simple Monte Carlo-type analysis can capture the effects of such variation. While high performance digital logic circuits, at high $V_{DD}$ , can be strongly affected by spatially correlated channel length variation, we note that subthreshold logic will be primarily affected by random uncorrelated $V_{T}$ variation.      

Modeling and Analysis of High-Speed I/O Links

Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A computationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topologies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design.      

Using Stochastic Differential Equation for Verification of Noise in Analog/RF Circuits

Today’s analog/RF design and verification face significant challenges due to circuit complexity, process variations and short market windows. In particular, the influence of technology parameters on circuits, and the issues related to noise modeling and verification still remain a priority for many applications. Noise could be due to unwanted interaction between the circuit elements or it could be inherited from the circuit elements. In addition, manufacturing disparity influence the characteristic behavior of the manufactured circuits. In this paper, we propose a methodology for modeling and verification of analog/RF designs in the presence of noise and process variations. Our approach is based on modeling the designs using stochastic differential equations (SDE) that will allow us to incorporate the statistical nature of noise. We also integrate the device variation due to 0.18μ m fabrication process in an SDE based simulation framework for monitoring properties of interest in order to quickly detect errors. Our approach is illustrated on nonlinear Tunnel-Diode and a Colpitts oscillator circuits.     

Random error effects in matched MOS capacitors and current sources

Explicit formulas are derived using statistical methods for the random errors affecting capacitance and current ratios in MOS integrated circuits. They give the dependence of each error source on the physical dimensions, the standard deviations of the fabrication parameters, the bias conditions, etc. Experimental results, obtained for both matched capacitors and matched current sources using a 3.5-/spl mu/m NMOS technology, confirmed the theoretical predictions. Random effects represent the ultimate limitation on the achievable accuracy of switched-capacitor filters, D/A converters, and other MOS analog integrated circuits. The results indicate that a 9-bit matching accuracy can be obtained for capacitors and an 8-bit accuracy for MOS current sources without difficulty if the systematic error sources are reduced using proper design and layout techniques.     

Computer-aided design considerations for mixed-signal coupling inRF integrated circuits

This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods     

An analytical method for direct calculation of E and H-fieldpatterns of conductor-backed coplanar waveguides

A new direct method of computing the electromagnetic field patterns surrounding the conductor-backed coplanar waveguide (CPW) structure is proposed. Analytical closed-form expressions describing the quasi-TEM field pattern in both the air and the dielectric substrate for conductor-backed CPW's are presented. This approach is based on a new technique which employs a series of inverse conformal mappings to transform a known field pattern from a rectangular structure back into the CPW structure in order to obtain its unknown field pattern directly. A computer program based on this method has demonstrated the speed at which the fields can be plotted compared to existing methods which require repetitive application. Graphical results of these field patterns are presented as a function of the CPW's geometry and dielectric substrate thickness. These held maps which have been directly drawn with true curvilinear squares enable the determination of power flow density, since the same power flows through each square. This direct method of characterizing the power flow density throughout the CPW structure could become an important design tool for the modeling of coplanar monolithic microwave integrated circuits (CMMIC's)     

CAD tools for efficient RF/microwave transistor modeling and circuit design

In today’s radiofrequency and microwave communication circuits, there is an ever-increasing demand for higher integration and miniaturization. This trend leads to massive computational tasks during simulation, optimization and statistical analyses, requiring robust modeling tools so that the whole process can be achieved reliably. In this paper, the authors proposed frequency- and time-domain computer-aided design tools that can characterize RF/microwave field effect and heterojunction bipolar transistors and efficiently predict a circuit performance. The proposed tools are demonstrated through examples.     

Robust minimum variance beamforming

This paper introduces an extension of minimum variance beamforming that explicitly takes into account variation or uncertainty in the array response. Sources of this uncertainty include imprecise knowledge of the angle of arrival and uncertainty in the array manifold. In our method, uncertainty in the array manifold is explicitly modeled via an ellipsoid that gives the possible values of the array for a particular look direction. We choose weights that minimize the total weighted power output of the array, subject to the constraint that the gain should exceed unity for all array responses in this ellipsoid. The robust weight selection process can be cast as a second-order cone program that can be solved efficiently using Lagrange multiplier techniques. If the ellipsoid reduces to a single point, the method coincides with Capon's method. We describe in detail several methods that can be used to derive an appropriate uncertainty ellipsoid for the array response. We form separate uncertainty ellipsoids for each component in the signal path (e.g., antenna, electronics) and then determine an aggregate uncertainty ellipsoid from these. We give new results for modeling the element-wise products of ellipsoids. We demonstrate the robust beamforming and the ellipsoidal modeling methods with several numerical examples.     

Spatial Filtering of Noninvasive Multielectrode EMG: Part II?Filter Performance in Theory and Modeling

Spatial filtering, particularly common in the field of engineering, is adapted in theory and practice to the filtering of propagating spatial EMG signals. This technique offers a new flexibility in the design of selective EMG measurement configurations. Longitudinal as well as two-dimensional spatial filters can be used. The conditions for the design of suitable spatial filters are deduced by signal theory. The performances of different selected configurations are compared by means of a given simple model of an excited motor unit. The modeling results compare well to the previously described experimental signals.     

Statistical Design of Low Power Square-Law CMOS Cells for High Yield

A robust design of low voltage low power square law CMOS composite cells using statistical VLSI design techniques is presented. Since random device/process variations do not scale down with feature size or supply voltage, the statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. The Response Surface Methodology and Design of Experiment techniques were used as statistical techniques. This article shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.     

数字图像空间分辨率改善的插值--模拟采样迭代方法

在遥感图像和计算机视觉的一些应用中,需要从已有的一些低分辨率图像来获得更高分辨率的图像.已有一些方法都是针对大小完全相同和图像之间不存在局部的几何畸变(或假设如此)的图像,而对从大小不同或分辨率不同的图像和图像之间存在相对的几何畸变等更普遍存在的实际图像来重构更高分辨率图像的问题未加涉及.本文用从带限信号的非均匀采样进行信号重构的迭代方法和凸集投影方法出发,导出了一种应用范围更加广泛的从多幅空间分辨率低的图像重构更高空间分辨率图像的一般性空间域插值-模拟采样迭代方法,并提出了凸集投影的变权迭代解法.该迭代方法可以对付图像之间存在相对的几何畸变、辐射亮度差异、空间分辨率差异及图像存在噪声等情形.实验表明,该迭代解法具有很好的收敛性和很好的收敛效果.     

Testability and test generation for majority voting fault-tolerant circuits

The testability of majority voting based fault-tolerant circuits is investigated and sufficient conditions for constructing circuits that are testable for all single and multiple stuck-at faults are established. The testability conditions apply to both combinational and sequential logic circuits and result in testable majority voting based fault-tolerant circuits without additional testability circuitry. Alternatively, the testability conditions facilitate the application of structured design for testability and Built-In Self-Test techniques to fault-tolerant circuits in a systematic manner. The complexity of the fault-tolerant circuit, when compared to the original circuit can significantly increase test pattern generation time when using traditional automatic test pattern generation software. Therefore, two test pattern generation algorithms are developed for detecting all single and multiple stuck-at faults in majority voting based circuits designed to satisfy the testability conditions. The algorithms are based on hierarchical test pattern generation using test patterns for the original, non-fault-tolerant circuit and structural knowledge of the majority voting based design. Efficiency is demonstrated in terms of test pattern generation time and cardinality of the resulting set of test patterns when compared to traditional automatic test pattern generation software.     

Using statistically designed experiments to improve reliability andto achieve robust reliability

This tutorial explains statistically designed experiments which provide a proactive means to improve reliability as advocated by Genichi Taguchi. That is, by systematic experimentation, the important parameters (factors) affecting reliability can be identified along with parameter values that yield reliability gains. In addition to improving reliability, Taguchi's robust design can be used to achieve robust reliability; that is, to make a process or product reliability insensitive to factors which are hard or impossible to control. Robust design is also implemented using statistically designed experiments. This paper presents classes of experimental plans for reliability improvement and robust reliability. An important feature of the reliability data collected from such experiments is censoring which occurs when some of the experimental units have not failed by the end of the experiment. Consequently, the analysis methodology must account for these censored data which are likely to occur in light of the ever increasing reliability of today's products. Several appropriate methods are discussed briefly. These experimental plans and analysis methods are illustrated using three documented experiments which improved fluorescent lamp and industrial thermostat reliability and which achieved robust reliability for night-vision goggles     

The IC yield problem: A tentative analysis for MOS/SOS circuits

Yield on integrated circuits is the result of the contribution of many parameters including number of masking steps, design dimensions, and intrinsic process steps. Test vehicles specific to each process to be investigated are used and through ring oscillators yield figures, and test pattern results, evaluation of yield, as well as identification of main causes of yield loss can be made. The test vehicle approach is consistent with actual LSI circuits yield figures. Defect densities for SOS and bulk processes are compared showing that they are mainly dependent upon the number of critical masking steps and design dimensions.