基于氧等离子体活化的硅硅直接键合工艺研究

基于氧等离子体活化的硅硅直接键合是一种新型的低温直接键合技术。为了优化工艺参数,得到高质量的键合硅片,选用正交试验法,研究了氧等离子体活化时间、活化功率、氧气流量三个重要的工艺参数对键合的影响,并采用键合率评估键合质量。研究结果表明,活化功率对键合率的影响最大,氧气流量次之,活化时间对结果影响最小,据此结论,在上述工艺中需重点关注活化功率和氧气流量的参数选择。     

Investigation of fluorine containing plasma activation for room-temperature bonding of Si-based materials

Wafer direct bonding of Si based materials, such as silicon, silicon oxide and silicon nitride, is a generic technique enabling realization of innovative structures in semiconductor industry. In this paper, a fluorine containing plasma activated bonding method is developed to achieve sufficient bonding at room temperature in air ambient with no heating process. The whole process is facile and cost effective without requiring high-vacuum system. It does work well for bonding of Si-based materials except for Si₃N₄/Si₃N₄ bonded pairs. The bonding strengths of specimens prepared by fluorine containing oxygen plasma are significantly improved at room temperature compared with those by oxygen plasma. The improved bonding strength is possibly attributed to the formation of fluorinated oxide layers on wafer surfaces after the plasma treatment.     

Study of thinned Si wafer warpage in 3D stacked wafers

3D (three-dimensional) wafer stacking technology has been developed extensively recently. One of the many technical challenges in 3D stacked wafers, and one of the most important, is wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within wafer (WIW) uniformity and even electrical failure. In this study, the wafer warpage of thinned Si wafers in stacked wafers has been evaluated. Si wafer or glass was used as a thick substrate, and Cu or polyimide was used as the bonding material. The top Si wafer in the bonded stack was ground down to 20–100 μm, and wafer curvature was measured. Wafer curvature and how it relates to bonding material, substrate material of the stacked layers, and thickness of thinned Si wafer will be discussed.     

Room temperature wafer bonding of silicon, oxidized silicon, and crystalline quartz

The use of plasma immersion as preparation for room temperature wafer bonding has been investigated. Silicon wafers have been successfully bonded at room temperature after exposure to oxygen or argon plasma. Oxidized silicon wafers and crystalline quartz have been bonded after exposure to oxygen plasma. The bonded interfaces exhibit very high surface energies, comparable to what can be achieved with annealing steps in the range of 600–800°C using normal wet chemical activation before bonding. The high mechanical stability obtained after bonding at room temperature is explained by an increased dynamic in water removal from the bonded interface allowing covalent bonds to be formed. Electrical measurements were used to investigate the usefulness of plasma bonded interfaces for electronic devices.     

Adhesion of NCF to oxidized Si wafers after oxygen plasma treatment

The effect of oxygen plasma treatment on the adhesion between nonconductive film (NCF) and oxidized Si was investigated. Oxidized Si wafers were treated with oxygen plasma for 5 min and then rinsed in de-ionized water (DIW). The water contact angle was measured by means of the sessile drop technique and the surface roughness was measured by means of atomic force microscopy. The adhesion of the NCF to the oxidized Si wafer was evaluated by means of a single-lap shear test after bonding at 150°C for 5 s. Oxygen plasma treatment decreased the water contact angle. The roughness of the oxidized Si wafer decreased when oxygen plasma treatment was applied alone, but was increased when both oxygen plasma treatment and DIW rinse were applied. Similarly, the shear strength decreased when oxygen plasma treatment was applied alone, but the adhesion of NCF increased when both oxygen plasma treatment and DIW rinse were applied. The increased surface roughness of the oxidized Si wafer played an important role in increasing the adhesion between the NCF and the oxidized Si wafer. The shear strength further increased after post-heat treatment at 170°C for 1 hr or at 280°C for 15 s. Low shear strength observed before post-heat treatment was ascribed to incomplete NCF curing. Differences observed in the adhesion strength between two types of NCF were attributed to differences in their curing degrees and their degrees of surface coverage of the oxidized Si substrates.     

Bonding silicon wafer to silicon nitride with spin-on glass as adhesive

Using spin-on glass (SOG) as an adhesive, an Si wafer with thermal oxide was successfully bonded to one with an RF-sputtered Si3N4 film. This ensures that SOG films are effective in bonding Si wafers to less reactive surfaces than Si or SiO2 such as silicon nitride. It was also found that the previously reported bonding procedure can be simplified by suppressing the spin-induced radial striations of the SOG films.     

Test Structures for the Characterization of MEMS and CMOS Integration Technology

Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical–mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8–5.2 $Omega $ have been obtained from via chain test structures and an average specific contact resistivity of 1.7$,times ,$10$^{-8} Omega {hbox{cm}}^{2}$ , measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.      

A Novel Bonding Method for Ionic Wafers

A novel method for bonding sapphire, quartz, and glass wafers with silicon using the modified surface activated bonding (SAB) method is described. In this method, the mating surfaces were cleaned and simultaneously coated with nano-adhesion Fe layers using a low energy argon ion beam. The optical images show that the entire area of the 4-in wafers of LiNbO₃/Si was bonded. Such images for other samples show particle induced voids across the interface. The average tensile strength for all of the mating pairs was much higher than 10 MPa. Prolonged irradiation reduced polarization in sapphire, quartz, and Al-silicate glasses. Fe and Ar ion-induced charge deposition result in the formation of an electric field, which was responsible for the depolarization. The lattice mismatch induced local strain was found in LiNbO₃/Si. No such strain was observed in the Al-silicate glass/Si interface probably because of annealing at 300 for 8 h. The Al-silicate glass/Si interface showed an interfacial layer of 2 nm thick. A 5-nm-thick amorphous layer was observed with the other layer across the /Si interface. The EELS spectra confirmed the presence of nano-adhesion Fe layers across the interface. These Fe layers associated with the electric field induced by ion beam irradiation for prolonged period of time, particularly in LiNbO₃/Si, might be responsible for the high bonding strength between Si/ionic wafers at low temperatures.     

InP and Si metal-oxide semiconductor structures fabricated using oxygen plasma assisted wafer bonding

In this paper, InP metal-oxide-semiconductor (MOS) structures are fabricated by transferring thermally grown SiO₂ to InP from oxidized Si wafers using oxygen plasma assisted wafer bonding followed by annealing at either 125°C or at 400°C. Well-defined accumulation and inversion regions in recorded capacitance-voltage (C-V) curves were obtained. The long-term stability was comparable to what has been previously reported. The structures exhibited high breakdown fields, equivalent to thermally grown SiO₂-Si MOS structures. The transferring process was also used to fabricate bonded Si MOS structures.     

用于聚合物基微流体MEMS的等离子体活性晶圆键合技术

Lab-on-chip或μ-TAS(micro-totalanalysissystems)结合流体处理、检测及数据分析,是一种便携式的低成本高效器件。在微流体应用中,聚合物具有比硅或玻璃器件更明显的优势,它包括:宽泛的材料选择性,成本低、效率高,使用任意性,生物兼容性,抗化学品和工艺灵活性。为了实现采用这类材料制备小型集成化系统,我们发展了新的制备与封装技术。这项工作着眼于运用等离子体活化低温直接键合技术实现纳/微结构聚合物在低温条件下进行封装。由纳米压印光刻制作的纳/微结构的聚合物器件,可能是异质(聚合物与玻璃或硅)或同质(聚合物与聚合物)键合。为了改进键合材料的物理和化学熔合,键合工序通常在接近聚合物的玻璃化转变温度的高温下进行。但遗憾的是,高温损伤了微细图形,特别是对于高深宽比结构。在EVG810LT 等离子体反应室里,我们采用软射频频率等离子体表面处理,来进行聚合物的等离子体活化,它能在不改变聚合物体特性的前提下清洗和活化聚合物顶层。最终结果是,在EVG501晶圆键合机上,两个活化的表面在低温下通过施加一个适中的、均匀的接触压力而连接在一起,保证了空腔密封并防止了小结构的破坏和变形。键合工艺条件为:真空条件为从大气到200~1000Pa、接触压力为2～5kN、温度从室温到80℃。RR     

基于Al2O3中间层的InP/SOI晶片键合技术研究

研究了基于Al2O3中间层的InP/SOI晶片键合技术.该方案利用原子层沉积技术在SOI晶片表面形成Al2O3作为InP/SOI键合中间层,同时采用氧等离子体工艺对晶片表面进行活化处理.原子力显微镜和接触角测试结果表明,氧等离子体处理使得晶片的表面特性更适于实现键合.透射电子显微镜和X射线能谱仪测试结果证实,采用Al2O3中间层可以实现InP晶片与SOI晶片的可靠键合.     

直接键合四结GaAs太阳电池研究

晶圆直接键合技术由于能将表面洁净的两个晶圆集成到一起,从而可以用来制备晶格失配 III-V族多结太阳电池。为了制备GaInP/GaAs/InGaAsP/InGaAs四结太阳电池,需采用具有低电阻率的GaAs/InP键合界面,从而实现GaInP/GaAs和InGaAsP/InGaA上下两个子电池的电学导通。我们设计并研究了具有不同掺杂元素和掺杂浓度的三种键合界面,并采用IV曲线对其电学性质进行表征。此外,对影响键合界面质量的关键工艺过程进行了研究,主要包括表面清洗技术和键合参数优化,例如键合温度、键合压力和键合时间等。最终制备出的键合四结GaInP/GaAs/InGaAsP/InGaAs太阳电池在AM0条件下效率最高达33.2%。     

Low temperature glass-to-glass wafer bonding

In this paper, results of successful anodic bonding between glass wafers at low temperature are reported. Prior to bonding, a special technique was used, i.e., an amorphous and hydrogen free silicon film was deposited on one of the glass wafers using a sputtering technique. The effects of bonding temperature and voltage were investigated. The bonding temperature and the voltage applied ranged from 200/spl deg/C to 300/spl deg/C and 200 V to 1000 V, respectively. As the bonding temperature and bonding voltage increased, both the unbonded area and the size of voids decreased. Scanning electron microscope (SEM) observations show that the two glass wafers are tightly bonded. The bond strength is higher than 10 MPa for all the bonding conditions. Furthermore, the bond strength increases with increasing bonding temperature and voltage. The study indicates that high temperature and voltage cause more Na/sup +/ ions to neutralize at the negative electrode, which leads to higher charge density inside the glass wafer. Furthermore, the transition period to the equilibrium state also becomes shorter. It is concluded that the anodic bonding mechanisms involve both oxidation of silicon film and the hydrogen bonding between hydroxyl groups.     

Nanoadhesion layer for enhanced Si–Si and Si–SiN wafer bonding

Direct wafer bonding of Si–Si and Si–SiN wafers was demonstrated using a nanoadhesion layer at room temperature. The two mating surfaces were cleaned by an Ar-ion beam and simultaneously deposited with ultrathin Fe layers (known as nanoadhesion layers). The ultrathin Fe layers imparted high bond strengths to Si–Si and Si–SiN bonds without heat treatment. Transmission electron microscopy revealed that the Si–Si and Si–SiN interfaces were tightly bonded and defect free. Moreover, the formation of crystalline iron silicide across the interface was found to enhance Si–Si wafer bonding. In addition to FeSi, an amorphous layer formed at the Si–SiN interface, resulting in a high bond strength at room temperature.     

Assessment of ultra-thin Si wafer thickness in 3D wafer stacking

3D integration with multi-stacked wafers is a promising option to enhance device performance and density beyond traditional device scaling limits. However, to bring wafer stacking into reality, there are many technological challenges to be resolved, and one of those is the problem of uniform Si wafer thinning. For multi-stacked devices, Si wafers must be drastically thinned down to less than 50 μm. Problems associated with such ultra-thin Si wafers range from basic wafer handling to difficulty in accurately assessing the thickness of the thinned wafer across the wafer. In this study, bonded wafer pairs have been prepared with different bonding materials, and the stacks were ground down to about 30 μm. The thickness of the ultra-thin wafers was measured by Fourier transform infrared spectrometry (FTIR) technique, and its stability based on bonding status as well as measuring issues will be discussed.     

Using Transmission Laser Bonding Technique for Line Bonding in Microsystem Packaging

The transmission laser bonding (TLB) technique has been developed for the formation of continuous line bonds for microsystem packaging applications. Line bonds are generated by overlapping single bonding spots, in which the degree of overlapping is achieved by varying the scanning speed of the laser as it irradiates the bonding wafers. An analytical model has been developed to guide the TLB process, attaining a uniform laser intensity that produces uniform bonds, satisfying the bonding requirements. Guided by this model, experiments have been conducted to bond Pyrex glass-to-Si wafers at various bonding conditions. To demonstrate the reliability of the technique and the model developed, the strength of the resulting bonded pairs has been evaluated by a micro tensile tester. At contact pressures higher than 1 MPa, the strength of bonded lines can reach a stable value of 9.2 MPa, which is comparable to those obtained by other major bonding processes. To further understand the associated bonding mechanism, the bonded interface has also been analyzed using auger electron spectroscopy and X-ray photoelectron spectroscopy, quantifying the drifting or diffusion of atoms that occurs between glass and Si wafers during the bonding process     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

Fluxless Wafer Bonding in Vacuum Using Electroplated Sn–Ag Layers

A wafer-to-wafer bonding process using Sn-Ag solder without any flux is successfully developed. This fluxless or flux-free feature makes void-free and uniform bonding layers possible. This is in contrast to the fluxing process employed in nearly all soldering processes adapted in the electronic industry. With the use of flux, the flux or flux residues are easily trapped in the solder joint, resulting in voids and uneven solder layers. This is particularly true if the bonding area is large, such as the entire wafer. Thus, void-free wafer bonding using solders has never been reported. It is thus clear that the key to achieve void-free wafer soldering is to eliminate flux completely. The new fluxless process is performed in a vacuum furnace built in house to inhibit solder oxidation. To prevent oxidation during solder manufacturing, a thin Ag capping layer is plated over the Sn layer right after the Sn layer is plated over an entire 2-in silicon wafer having Cr/Au under bump metallurgy (UBM). This outer Ag layer is critical in preventing the inner Sn layer from oxidation when the wafer is exposed to air. The Si wafer with Cr/Au/Sn/Ag structure is bonded with another Si wafer with Cr/Au at 240degC in the vacuum furnace. To evaluate the joint quality and study the microstructure and composition, scanning acoustic microscopy (SAM), scanning electron microscopy (SEM), and energy dispersive X-ray spectroscopy (EDX) are used. A solder joint with only 1% void area is accomplished. The initial success of this process illustrates that it is indeed possible to bond entire wafers together with a thin metallic joint of high quality. This fluxless bonding technique can be extended to bonding wafers of different materials for new device and packaging applications.     

Evaluation of wafer bonding and etch back for SOI technology

Film quality and crystalline perfection of SOI layers obtained by bonding and etch back silicon-on-insulator (BESOI) technology have been studied. In particular, the various mechanisms of defect generation that contribute to a degradation of the original bulk Si quality in the superficial Si layer of such SOI structures have been investigated. Utilizing transmission x-ray topography combined with transmission electron microscopy (TEM), the critical processing parameters causing defect generation have been identified and the principal mechanisms of dislocation nucleation have been elucidated. Strain compensated bonded SOI wafers have also been evaluated by non-destructive elastic light scattering and optical beam induced current (OBIC) to obtain topographic defect maps of entire SOI wafers. This analytical technique has the capability to comprehensively characterize surface and subsurface morphological features which result from the bonding and thinning processing steps. A comparison of wafer bonding and etch back technology with different etch stop fabrication techniques is presented. In this review, it is demonstrated that the presence of a boron-doped etch stop layer, with its accompanying lattice contraction and strain compensation, represents a key difference in the observed morphological patterns of bonded SOI wafers.     

Characteristics of new dielectric isolation wafers for high voltagepower IC's by single-Si poly-Si direct bonding (SPSDB) technique

Physical and mechanical characteristics of a new DI (Dielectric Isolation) wafer based on a single-Si poly-Si direct bonding (SPSDB) technique were investigated to reduce wafer warpage, increase wafer size and decrease minimum device patterning size. Developed SPSDB wafers of 5-inch size had unchanging warpage height and high bonding strength. When SPSDB wafers were bonded at 1100°C for 2 h, the latter property was comparable to that of the thermal oxidizing layer interface