基于暂态电流的高压输电线的故障检测

针对高压输电线故障存在检修困难、故障点定位误差较大和易受外部因素影响等问题,本文根据行波传输理论以故障电流行波为测量对象,提出一种基于暂态电流的高压输电线路单端故障测距算法。现以某区电网高压输电线路故障为例,利用MATLAB构建仿真模型进行仿真。由仿真结果可以看出：所采用的故障测距算法不仅计算简单,而且测距精度较高。     

Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction

Eliminating the excessive test power for integrated circuits is a strict challenge within the nanometer era. This method combines test pattern generation with the scan chain disabling technique to achieve low capture power testing under the single stuck-at fault model. Testability analysis is exploited to assist in the test pattern generation process to generate the observation-oriented test patterns. In order to direct fault effects to the frequently-used circuit outputs, unbalanced observability costs are purposely assigned to circuit outputs to introduce unequal propagation probability. Observation-aware scan chain clustering is then performed through a weighted compatibility analysis to densely cluster the frequently-used scan cells into scan chains. Consequently, more scan chains can be disabled in the capture cycle and significant power reduction can be achieved without affecting the fault coverage. To simultaneously consider the reduction in large test data volume and capture power, the power-aware test vector compaction algorithm is also performed. Experimental results for the large ISCAS’89 benchmark circuits show that significant improvements can be simultaneously achieved including 71.7 % of capture power reduction, 43.7 % of total power reduction, 24.3 % of peak power reduction and 98.0 % of test data compaction ratios averagely. Results for three large ITC’99 benchmark circuits also demonstrate the effectiveness of the proposed method for the practical-scale circuits.     

基于Upwind差分格式的电缆故障测距仿真系统

波反射法是目前电力电缆故障测距的主要方法,而波反射法采集到的故障波形复杂多变,分析较为困难。因此利用电缆的传输线模型,在分析偏微分方程数值解理论的基础上,提出了基于Upwind差分格式来进行传输线时域分析,并由此建立电缆故障测距仿真系统。检修人员通过仿真软件,学习分析电缆故障测距中可能出现的各种波形,可以提高工程实际中故障点的判断能力。仿真结果表明,仿真波形与工程实际中测试到的故障波形基本一致,能够很好地用于对电缆故障检修人员进行培训。     

A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing

This paper presents a 0.35-μm CMOS on-chip spectrum analyzer based on switched-capacitor (SC) techniques. The prototype device utilizes a 3-V supply and basically includes an SC sine-wave generator, a fourth-order high-selectivity SC filter, and a programmable gain amplifier followed by an 8-b analog-to-digital converter. A non-uniform sampling scheme, which adds one degree of freedom in determining the frequency response parameters of SC circuits, helps to obtain high programmability resolution without modifying any capacitor value. As a result, capacitor spread and total capacitor area are reduced as compared to traditional SC solutions and, hence, test area overhead is minimized. Experimental results demonstrate the effectiveness of the proposed approach to perform frequency response and total harmonic distortion measurements for frequencies up to 1 MHz.     

Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware

This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a circuit which implements a closest-match fault location algorithm specialized for the circuit under diagnosis (CUD). This method allows designers to perform dynamic fault location of stuck-at faults in large circuits, and eliminates the need for large storage required by a software-based fault dictionary. In fact, the approach is a pure hardware solution to fault diagnosis. We demonstrate the feasibility of the method in terms of hardware resources and diagnosis time by experimenting with ISCAS85 and ISCAS89 circuits. The emulation-based diagnosis method speeds up the diagnosis process by an order of magnitude compared to the software-based fault diagnosis. This speed-up is important, especially, when the on-line diagnosis of safety–critical systems is of concern.

具有容差的模拟电路故障定位的神经网络实现

结合Ｋ故障诊断和ＢＰ网络的分类功能,提出了一种神经网络实现模拟故障定位的方法,该方法将ＢＰ网络训练成具有推广能力的广义故障字典。     

A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs

Using multiple-valued logic provides more information transmission over a signal line. So it could solve the binary logic circuits problems such as interconnections requirement. In this paper, a universal method for designing ternary 3-2 and 4-2 compressor cells based on carbon nanotube field-effect transistors (CNTFETs) is presented. The proposed circuits use unique properties of CNTFETs, such as adjustable threshold voltage by changing CNT diameter and ballistic carrier transportation. In both designs transmission gates, ternary decoder and standard ternary buffers with different threshold voltages are used. The proposed compressors receive three (for 3-2 compressor) or four (for 4-2 compressor) ternary digits, produce the summation of these digits and show the results in two ternary digits (Sum, Carry). For evaluation and simulation the proposed circuits, Synopsys HSPICE simulator with 32 nm compact model is used in different simulation conditions.     

Compact formulation for exact analysis of nonideal SC circuits

A systematic analysis procedure to obtain closed-form expressions for the z-domain transfer functions of SC circuits with finite GB product op-amps is presented. This method allows exact frequential analysis of a general class of SC circuits, without imposing any restriction in the ratio between GB and clock frequencies.     

Test of a switched-capacitor ADC by a built-in charge sensor

A test methodology for switched capacitor circuits is described. The test approach uses a built-in sensor to analyze the charge transfer inside the circuit under test (CUT). The test methodology is applied to a 10-bit algorithmic analog to digital converter to obtain the static linearity and to the simulated fault coverage figures taking into account a catastrophic fault model. The goodness of the charge sensor has been experimentally evaluated with an SC integrator for fault detection and built-in sensor influence on the CUT performance.     

Fault prediction for analog circuits

The main problems that are the major concern in network testing are fault detection, fault location, and fault prediction. In this paper a multiple-fault-prediction algorithm is proposed for analog circuits with inaccessible nodes. The components in the circuits may be nominals or may be deviated from the nominals within a prescribed tolerance.In the proposed prediction algorithm, the component values are evaluated according to the consecutive voltage measurements that are continuously monitored at the accessible test points at each periodic maintenance. The component values are used to locate the faulty components and/or to predict the components that are about to fail.This research was supported in part by AURI, Michigan State University, East Lansing, Michigan, and in part by Michigan Research Excellence/Economic Development Fund.     

基于MST框架的PCNN输电线路红外热故障区域提取方法

针对输电线路电气设备红外热故障检测,提出采用一种基于最大相似度阈值（Maximum Similarity Thresholding, MST）的脉冲耦合神经网络（Pulse-coupled neural Network, PCNN）红外图像热故障区域提取方法。在该方法中,利用脉冲耦合神经元对相似的邻域神经元同步点火特性,通过引入最大相似度阈值框架,简化了PCNN模型的阈值设置机制。同时,针对相似邻域神经元的同步点火特性,采用最小聚类方差设置连接系数,使得PCNN模型在自适应迭代下最终获取热故障区域。最后通过真实输电线路电气设备红外故障图像测试,验证了文中所提方法的有效性和适用性,为PCNN模型的推广应用奠定了基础。     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

非均匀有耗传输线ABCD参量的求解

传输线理论是射频与微波电路的重要基础理论,而其中ABCD参量特别适用于分析级联网络的传输性能.本文针对非均匀有耗传输线的ABCD参量求解问题,建立传输线的数学模型,给出了三种解法,即级联法、微分方程法和积分方程法,并对三种方法的准确性和效率进行了讨论.     

Synthesis method for testable electrical networks using 1st order building blocks

This work presents a method for synthesizing testable continuous-time linear time-invariant electrical networks using 1st order blocks for the implementation of analog linear circuits. A functional-structural fault model for the block, and a fault dictionary are proposed together with a simple set of test vectors. The method allows, also, the fault grade evaluation for the modeled faults. The results obtained from the two application examples have shown the suitability of the approach as a design for test method for analog circuits.     

在牵引网中一种新的故障测距法的应用研究

研究了将高压输电线中利用故障电流分量消除过渡电阻影响的阻抗测距原理用于单边供电的牵引网馈线故障测距的算法。根据实际可能存在的机车与故障点的相对位置，分牵引网上无负荷电流、有负荷电流且牵引网故障点发生在机车与变电所之间、有负荷电流且故障点发生在机车与变电所以外的3种情况分别进行了仿真，仿真结果证明此法用于牵引网故障测距较常规阻抗测距法测距精度将大大提高。     

Distributed circuit design with transmisssion line elements

A short length of transmission line can be chosen as a basic circuit element. Systems containing such elements can then be synthesized to do an amazing number of things. For example, commensurate lines, all multiples of a given length with differing characteristic impedances but with common propagation constant, can be interconnected to realize microwave filters, broad-band transformers, broad-band delay lines with amplitude selectivity, and distributed RC structures. The fundamental ideas underlying the synthesis of commensurate transmission line circuits are presented in this paper in a tutorial fashion. The presentation is based on the scattering formalism and Richard's Theorem. The discussion is liberally sprinkled with design illustrations chosen from current practice.     

微波单片模拟电路CAD软件

本文介绍清华电子系正在研制的一部大型微波单片集成电路CAD软件.该软件用于MMIC及MIC模拟电路的分析与优化设计,主要可进行低噪声放大、宽频带放大、功率放大、混频、滤波、天线及匹配网络等电路设计.针对MMIC的特点,采用了多种先进的数值分析方法.在元件分析方面使用了场匹配法、直线法、模型法;电路方面采用元件灵敏度分析、矩量法全电路分析、谐波平衡非线性分析、蒙特卡洛成品率分析;优化技术上利用全域随机优化、梯度优化、灵敏度优化等.经计算与验证,该软件精度高、效果好、使用方便.目前仍在进一步开发研究.     

Exact reliability analysis of combinational logic circuits

A novel method is presented for the exact reliability analysis of combinational logic circuits. A model is developed that allows the logic circuit to be presented by a circuit equivalent graph (CEG). The reliability is analyzed by a systematic searching of certain subgraphs from the CEG. A computer algorithm and an example are given. The method gives the exact solution to the combinational logic circuit reliability-analysis problem. This is achieved by proper gate/circuit modeling, which allows the enumeration of all redundant fault vectors in a given circuit. Due to the concept of dominance among fault vectors, the number of necessary enumerations is appreciably reduced, and thus circuits with a few tens of gates can be efficiently analyzed     

基于二分图模型的通信信息网络故障联合定位

国家电网信息通信网络依靠两套运维系统,分别实现对信息网络与通信网络的故障定位与分析,然而通信网络故障往往会引发信息网络故障,如何高效精确地进行通信信息网络故障联合定位是亟需解决的问题.针对信息通信网络的联合故障定位问题,提出了基于二分图模型的故障联合定位算法.首先依据通信网网络节点的关联性对网络分簇,并将每一簇作为一个子域.其次在每个子域内建立基于二分图的故障关联影响模型,最终利用目标排序法并行地对多个子域内网络故障进行分析,从而实现通信信息网络关联故障高效精确的联合定位.实验结果表明,该联合故障定位分析方法的故障诊断率达85％～95％.