Statistical timing and power analysis of VLSI considering non-linear dependence

Majority of practical multivariate statistical analysis and optimizations model interdependence among random variables in terms of the linear correlation. Though linear correlation is simple to use and evaluate, in several cases non-linear dependence between random variables may be too strong to ignore. In this paper, we propose polynomial correlation coefficients as simple measure of multi-variable non-linear dependence and show that the need for modeling non-linear dependence strongly depends on the end function that is to be evaluated from the random variables. Then, we calculate the errors in estimation resulting from assuming independence of components generated by linear de-correlation techniques, such as PCA and ICA. The experimental results show that the error predicted by our method is within 1% error compared to the real simulation of statistical timing and leakage analysis. In order to deal with non-linear dependence, we further develop a target-function-driven component analysis algorithm (FCA) to minimize the error caused by ignoring high order dependence. We apply FCA to statistical leakage power analysis and SRAM cell noise margin variation analysis. Experimental results show that the proposed FCA method is more accurate compared to the traditional PCA or ICA.     

Modelling noise and delay in VLSI circuits

New models for estimating delay and noise in VLSI circuits, based on closed form expressions for the first and second moment of the impulse response in coupled RC trees are reported. The effect of crosstalk on delay and noise can be accurately estimated with a complexity only marginally higher than the Elmore delay.     

Eliminating inductive noise of external chip interconnections

On-chip balanced drivers can essentially eliminate inductive noise, without any power dissipation penalty, and independently of the number of chip drivers switching simultaneously or the switching speed. In addition, balanced interconnections on PWBs and MCMs substantially reduce crosstalk, increase noise immunity, and eliminate ground noise     

Estimating power dissipation in VLSI circuits

With the shift to low power IC design for personal computing and communication applications, designers' priorities turn to accurate and efficient estimation of power consumption in ICs. Traditional current and power estimation techniques based on a SPICE-like simulation do not provide the necessary efficiency for such an application, and thus new approaches have been recently proposed. In this, the first of a series of articles that reflect the new orientation of this column, Professor Farid Najm of the University of Illinois at Urbana-Champaign presents an overview of different techniques for estimating power consumption in large-scale IC designs. He also discusses computer aided design tools to help in the task     

Measurement of inductive coupling between coplanar superconductingtransmission lines

By measuring forward and backward coupling between superconducting coplanar transmission lines at various temperatures, we determined the dependence of inductive coupling on the London penetration depth. If the transmission lines are separated by a shielding ground line, inductive coupling increases with increasing penetration depth. If the shielding line is damaged or absent, there is a slight decrease. Since both effects are in the percentage range, they can only be observed in the forward-coupled noise signal. The backward coupled noise is nearly temperature independent. We measured inductive coupling factors between 6 and 8% on 10- and 5-μm-wide transmission lines, which are separated by a shielding ground line. Excellent agreement was obtained between measurements and FEM simulations     

Hybrid analytical modeling of noise coupling to signal traces in a power bus with embedded film capacitor

An accurate hybrid analytical method is proposed to determine the coupling of switching noise to signal traces in a multilayer power bus with embedded film capacitor. We used the induction equivalent theorem to derive the solution of noise coupling and the segmentation method to calculate the electric field of the noise in a power bus. The proposed method was verified by measurements of impedance parameters in the frequency domain.     

Efficient shield insertion for inductive noise reduction in nanometer technologies

With high clock frequencies, faster transistor rise/fall time, wider wires, and the use of Cu material interconnects, interconnect inductive noise is becoming an important design metric in digital circuits. An efficient technique to reduce the inductive noise of on-chip interconnects is to insert shields among signal wires. An efficient solution for the min-area shield insertion problem to satisfy given explicit noise bounds in multiple coupled nets is provided. The proposed algorithm determines the locations and number of shields needed to satisfy certain noise constraints. Experimental results show that the proposed approach minimizes the number of shields required to satisfy the noise constraints and uses less runtime than the best alternative reported approach.     

松耦合感应电能传输效率分析

首先给出了非接触式松耦合感应电能传输的基本原理 ,电路结构采用半桥串联谐振电路,并用电容串联补偿,通过系统数学建模,把电路分为串联谐振变换器和整流电路两个部分,然后详细讨论了影响系统电能传输效率的关键因素.基于以上的分析讨论后,最后给出此类松耦合感应电能传输系统设计方法.     

The impact of process noise on VLSI process improvement

Process improvement is critical to commercial success in VLSI fabrication, especially during ramp-up. This paper investigates one of the factors-process noise-that drives the success of process improvement. Split-lot controlled experiments are vulnerable to confounding by experimental noise, caused by process variability. Fabs with low noise levels have a higher potential for learning (and hence improving their production processes) than high noise fabs. Detailed probe yield data from five semiconductor fabs were examined to estimate process noise levels. A bootstrap simulation was used to estimate the error rates of identical controlled experiments conducted in each fab. Absolute noise levels were high for all but the best fabs, leading to lost learning. The magnitude of lost learning is estimated numerically; it ranges from ten percent to above one hundred percent of the theoretically possible learning in an experiment. In some cases, experiments are little better than coin flipping. Standard statistical methods are either expensive or ineffective for dealing with these high noise levels. Some alternative nonstatistical countermeasures are recommended     

Transaction-level power analysis of VLSI digital systems

The increasing complexity of VLSI digital systems has dramatically supported system-level representations in modeling and design activities. This evolution makes often necessary a compliant rearrangement of the modalities followed in validation and analysis tasks, as in the case of power performances estimation.Nowadays, transaction-level paradigms are having a wider and wider consideration in the research on electronic system-level design techniques. With regard to the available modeling resources, the most relevant framework is probably the transaction-level extension of the SystemC language (SystemC/TLM), which therefore represents the best platform for defining transaction-level design techniques.In this paper we present a macro-modeling power estimation methodology valid for SystemC/TLM prototypes and of general applicability. The present discussion illustrates the implementation modalities of the proposed approach, verifying its effectiveness through a comparison with RTL estimation techniques.     

Study on crosstalk in inductive transmission of power andinformation

In previous papers, the authors introduced the wireless transmission of power and information (WTPI). This paper describes the most important issue for realizing the WTPI, which is how to ensure reliable transmission by reducing the crosstalk from the power-to-data channel. Crosstalk analysis is made with the following steps after the review of the WTPI technology: (1) magnetic flux distribution in the coaxial WTPI coupling is assumed; (2) an equivalent circuit is drawn by introduction of the crosstalk coefficient K_ct; and (3) according to the equivalent circuit, the crosstalk ratio CR is calculated and the induced noise level is estimated. Thereafter, the following three possible countermeasures to reduce crosstalk are proposed: (1) appropriate magnetic core dimensioning for the coupling; (2) reduction of high-frequency harmonics in the power inverter output voltage; and (3) magnetic shielding. Lastly, test results on concurrent transmission with the combination of these countermeasures are shown     

A survey of power estimation techniques in VLSI circuits

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed     

Peak power estimation of VLSI circuits: new peak power measures

New measures of peak power are proposed in the context of sequential circuits, and an efficient automatic procedure is presented to obtain very good lower bounds on these measures, as well as providing the actual input vectors that attain such bounds. Automatic generation of a functional vector loop for near-worst case power consumption is also attained. Experiments show that vector sequences generated give much more accurate estimates of peak power dissipation and are generated in significantly shorter execution times than estimates made from randomly generated sequences for four delay models     

Suppression of GHz range power/ground inductive impedance and simultaneous switching noise using embedded film capacitors in multilayer packages and PCBs

We measured and demonstrated the great advantages of embedded film capacitors in reducing power/ground inductive impedance and the suppression of SSN at frequencies up to 3 GHz for high-performance multilayer packages and PCBs. Eight-layer test PCBs were fabricated, and their inductive power/ground network impedances were measured as a function of film thickness, via distribution, and combined use with discrete decoupling capacitors, using a two-port self-impedance measurement method. This successfully demonstrated that the power/ground inductive impedance was reduced from 270 pH to 106 pH simply by using an embedded film capacitor instead of 16 discrete decoupling capacitors.     

Quantifying and enhancing power awareness of VLSI systems

An increasingly important figure-of-merit of a VLSI system is "power awareness," which is its ability to scale power consumption in response to changing operating conditions. These changes might be brought about by the time-varying nature of inputs, desired output quality, or just environmental conditions. Regardless of whether they were engineered for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that some systems are "more" power aware than others. Equivalently, we should be able to re-engineer systems to increase their power awareness. In this paper, we attempt to quantitatively define power awareness and how such awareness can be enhanced using a systematic technique. We illustrate this technique by applying it to VLSI systems at several levels of the system hierarchy - multipliers, register files, digital filters, dynamic voltage-scaled processors, and data-gathering wireless networks. It is seen that, as a result, the power awareness of these preceding systems can be significantly enhanced leading to increases in battery lifetimes in the range of 60-200%     

Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise

In this paper, we present an algorithm for computing the bounds on energy-efficiency of digital very large scale integration (VLSI) systems in the presence of deep submicron noise. The proposed algorithm is based on a soft-decision channel model of noisy VLSI systems and employs information-theoretic arguments. Bounds on energy-efficiency are computed for multimodule systems, static gates, dynamic circuits and noise-tolerant dynamic circuits in 0.25-/spl mu/m CMOS technology. As the complexity of the proposed algorithm grows linearly with the size of the system, it is suitable for computing the bounds on energy-efficiency for complex VLSI systems. A key result presented is that noise-tolerant dynamic circuits offer the best trade off between energy-efficiency and noise-immunity when compared to static and domino circuits. Furthermore, employing a 16-bit noise-tolerant Manchester adder in a CDMA receiver, we demonstrate a 31.2%-51.4% energy reduction over conventional systems when operating in the presence of noise. In addition, we compute the lower bounds on energy dissipation for this CDMA receiver and show that these lower bounds are 2.8/spl times/ below the actual energy consumed, and that noise-tolerance reduces the gap between the lower bounds and actual energy dissipation by a factor of 1.9/spl times/.     

Temporal frequency dependence of modal noise in fibres

For a particular source and fibre, frequency correlation effects determine speckle contrast. For a specified degree of spatial filtration, speckle contrast in turn determines modal noise statistics. The measurement and analysis is reported of the correlation of two multimode fibre speckle patterns as a function of their source frequency difference.     

High-frequency dependence of channel noise in short-channel RFMOSFETs

Using a two-dimensional (2-D) Green's function technique, similar to Shockley's impedance field technique, simulation results of the drain i_d and gate induced i_g channel noise are presented for an nMOS transistor as a function of frequency. The simulation results show that for frequencies much lower than the cutoff frequency of the transistor f_t the correlation factor (i.e., i¯ _g¯i¯*_d¯/√i_g^-2 i_g^-2) between the drain and gate channel noise is equal to approximately 0.4j. For frequencies near the f_t of the device the correlation factor approximately equals 0.3j. For f/f_t~0.3, the contribution of the gate induced noise compared to the drain noise was found to be on the order of 1% (i.e., i _g^-2/i_d^-2(f_t/f) ²)     

Frequency properties of on-die power distribution network in VLSI circuits

The local voltage fluctuations in the supply and ground grids triggered by on-die logic cell switching in VLSI devices have been experimentally studied. The results show that these fluctuations have a resonant-like form i.e., the on-die power grid should be described as an RLC circuit. The studies reveal that the active element (i.e., CMOS logic cell) affects the frequency properties of power supply and ground grids during its switching (as opposed to before or after switching). It is demonstrated that the frequency properties of the both grids are inter-related via the interconnecting active elements.