2.488 Gb/s SONET multiplexer/demultiplexer with frame detectioncapability

The authors describe a novel scheme that allows a demultiplexer, a byte aligner, and a frame detection circuit tube to be integrated on one chip without compromising the demultiplexer's performance. A research prototype integrated circuit (IC) that incorporates this scheme was designed to operate at speeds up to the SONET STS-48 (synchronous transport signal level 48) rate of 2.488 Gb/s. The IC is implemented in GaAs enhancement/depletion mode MESFET technology, and it performs 1:8 demultiplexing, byte alignment, and SONET frame detection functions. A separate IC that performs 8:1 multiplexing was also implemented using the same technology. The bit error rate; test results show that the multiplexer and demultiplexer with frame detector can operate at 2.488 Gb/s with a bit error rate less than 1×10^-14. Both ICs were tested at data rates up to 3 Gb/s     

OC-12/STS-3c/ATM interface for gigabit network applications

The implementation of an experimental OC-12/STS-3c/ATM transmission interface is described. This interface maps four streams of ATM cell data into the SONET STS-3c transmission format and multiplexes these channels onto a single OC-12 (622 Mbit/s) optical signal. The interface also performs the reverse demultiplexing functions. This application represents the first known demonstration of a 622 Mbit/s ATM workstation interface.<>     

50-Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial communication systems

4:1 multiplexer and 1:4 demultiplexer ICs targeting SONET OC-768 applications are reported. The ICs have been implemented using a 120-GHz-f/sub T/ 0.18-/spl mu/m SiGe BiCMOS process. Both ICs have been packaged to enable bit error rate testing by connecting their serial interfaces. Error-free operation has been achieved for both circuits at data rates beyond 50 Gb/s. At a -3.6-V supply voltage, the multiplexer and demultiplexer dissipate 410 and 430 mA, respectively. Switching behavior of the 4:1 multiplexer has also been checked up to 70 Gb/s.     

An economic feasibility study for a broadband virtual pathSONET/ATM self-healing ring architecture

A ring architecture that uses the asynchronous transfer mode (ATM) virtual path (VP) concept to reduce the SONET ring cost in terms of bandwidth management is discussed. The add-drop multiplexer (ADM) proposed for VP ring architectures can evolve from existing SONET ADMs by replacing the STS-3 termination cards by the ATM STS-3c line cards. Existing standard self-healing schemes and protocol SONET rings can be applied to proposed ATM/SONET VP rings. A case study based on a BCC (Bellcore client company) ring network and the sensitivity analysis suggests that the proposed ATM VP ring architecture may be a cost-effective option for implementing the distributed ring grooming system at the DS 1 level. The proposed VP self-healing rings are not only used to carry existing DS 1 and DS 3 service, but can also be used to more cost-effectively consolidate switches for public-switched services and for SMDS, frame relay, and FDDI in metropolitan areas     

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.     

2.5Gb/s SDH/SONET传送开销处理器芯片实现

设计了一种2.5Gb/s同步光纤网络SDH/SONET中传送开销处理器芯片.采用双向4路总线流水线结构,77.76MHz的系统时钟,即可实时处理2.5Gb/s的SDH/SONET数据.支持STM-16、4路STM-4和STM-1的再生段开销和复用段开销处理以及STS-48、4路STS-12和STS-3的段开销和线路开销处理.采用TSMC 0.13μm工艺流片,电路规模约48万门,技术指标符合ITU-T标准.     

PDH到622Mb/sSDH/SONET映射芯片实现

 设计了PDH到622 Mb/s SDH/SONET的映射及逆映射芯片.集成了DS1/E1/J1成帧器、DS1/DS3复接电路和E1/E3复接电路,具有622 Mb/s和155 Mb/s的高速标准接口和3通道STM-1/STS-3分插复用总线接口,支持复用段1+1保护和UPSR环形网络拓扑结构.单片实现84通道DS1/J1或63通道E1到STM-1/STS-3的映射复用功能及多通道DS3/E3/STS-1到STM-4/STS-12的映射复用功能.支持点对点应用和环形应用,交换模式支持2016通道DS0/E0的应用.4颗芯片实现336通道DS1/J1或252通道E1到STM-4/STS-12的映射复用功能.采用TSMC 0.13 μm CMOS工艺流片,芯片规模约600万门,700管脚 PGBA封装,满足光纤通信传输的要求,并成功用于光纤通信设备.     

A SONET STS-3c user network interface integrated circuit

Two different design implementation techniques were used to produce a functionally complex high performance synchronous optical network (SONET) synchronous transmission signal (STS)-3c (155.52 Mb/s) user network interface (UNI) chip in cost-effective 1 μm CMOS technology. The CMOS chip functions as an STS-3c transmitter and receiver and can interface to the STS-3c line in either bit-serial or byte-parallel data format. The transmitter creates a SONET STS-3c frame structure including the necessary framing and control bytes. The receiver performs frame detection, several performance monitoring functions, and payload processor interpretation. In addition to SONET overheads, both the transmitter and receiver provide payload asynchronous transfer mode (ATM) mapping signals to the user. The user can choose between serial operation at 155.52 Mb/s or parallel operation at 19.44 Mbyte/s. Test results show that the experimental integrated circuit performs successfully at serial data rates of up to 300 Mb/s     

Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect andadd/drop multiplexer solution

This paper presents a single-chip all-CMOS solution for 4×OC-3c, OC-12, and OC-12c synchronous digital hierarchy/synchronous optical network (SDH/SONET) framing with integrated serial line interfaces. Outstanding features of this chip are clock and data recovery and fulfillment of ITU-T and Bellcore jitter requirements for SDH/SONET systems, as well as the large range of functions offered. These functions include asynchronous transfer mode (ATM) and point-to-point protocol (PPP) support, as well as built-in native SDH/SONET functions such as digital cross-connect, add/drop multiplexing, and automatic protection switching. In addition, the chip is based on a new scalable modular architecture     

Design and characterization of an error-correcting code for theSONET STS-1 tributary

The authors have designed and characterized a single-error-correcting (SEC), double-error-detecting (DED) code applicable to the STS-1 SONET format. They show that if two of the presently unallocated bytes in the path overhead field of STS-1 are assigned for error-correction coding (ECC), a {6208, 6195} shortened extended Hamming code can be implemented using as few as 660 gates plus a 1-kbyte RAM IC, achieving (O8.6×10^-3 P ₂²) BER reduction with 139 μs of signal delay. The authors explain how the existing BIP-8 error-monitoring byte of the STS-1 format could be integrated with the proposed ECC so that a net allocation of only one new STS-1 overhead byte is required for both error monitoring and error correction. The implementation method is such that all path, line, and section overhead functions in SONET can be performed at intermediate sites without requiring ECC decoding. The authors consider application alternatives and describe the forward-error-correction (FEC) circuit design and trial results. System issues are covered, including network delay, effects of error extension on BER, addition of double-error detection, performance monitoring, and options for intelligent network control and management of FEC functions. Codes related to their path-level design that are applicable to a number of other strategies for applying FEC in SONET are presented     

光通信用10Gbit/s Transponder的设计

本文分析了在高速光模块设计中介质损耗和微带结构对信号的影响,并对PCB中信号串扰模型的参数进行了计算.解决了高速光模块设计的一些关键问题,设计出满足MSA的300-pin transponder,并对模块进行了一系列性能和指标测试.测试结果表明,该模块完全满足SDH/SONET(STM-64/OC-192)以及10G Ethernet应用要求.     

10 Gb/s silicon bipolar 8:1 multiplexer and 1:8 demultiplexer

High-speed multiplexer and demultiplexer circuits are key components in high-speed optical communication systems such as SONET. As optical communication link speeds increase, faster electronic interface circuitry is required. The use of multiplexer circuits allows most of the electronic circuitry to operate on parallel data at a lower speed, reducing the speed requirements of much of the system. A retimed 8:1 multiplexer and a 1:8 demultiplexer which operate at 10 Gb/s are described. These circuits were fabricated in high-speed silicon bipolar process. Design optimization techniques were used to achieve maximum performance. The retimed multiplexer and the demultiplexer dissipate 3.8 and 4.3 W, respectively     

A 10-GB/s SONET-compliant CMOS transceiver with low crosstalk and intrinsic jitter

A 4:1 SERDES IC suitable for SONET OC-192 and 10-Gb/s Ethernet is presented. The receiver, which consists of a limiting amplifier, a clock and data recovery unit, and a demultiplexer, locks automatically to all data rates in the range 9.95-10.7 Gb/s. At a bit error rate of less than 10/sup -12/, it has a sensitivity of 20 mV. The transmitter comprises a clock multiplying unit and a multiplexer. The jitter of the transmitted data signal is 0.2 ps RMS. This is facilitated by a novel notched inductor layout and a special power supply concept, which reduces cross-coupling between the transmitter and receiver. Integrated in a 0.13-/spl mu/m CMOS technology, the total power consumption from both 1.2- and 2.5-V supplies is less than 1 W.     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

Simulation and design methodology for a 50-Gb/s multiplexer/demultiplexer package

A 50 Gb/s package for SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer targeting SONET OC-768 serial communication systems is introduced in this work. The package was designed to facilitate bit-error-rate tests and constructed with high-speed coaxial connectors, transmission lines on ceramic substrate, ribbon bonds for chip-to-package interconnects, and a metal composite housing. Numerical simulations were conducted to guide the package design, and both small signal measurements and operational tests were performed thereafter to verify the design and modeling concepts. To keep the model structure under the existing computing capability, the simulation was segmented into three sections - coaxial connector to transmission line, transmission line alone, and transmission line to ribbon bond, and then the results were assembled to predict the performance of the entire package. The package was operated up to 50 Gb/s with low degradation to input digital waveforms and free of error.     

A 0.18-/spl mu/m SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems

A 43-Gb/s receiver (Rx) and transmitter (Tx) chip set for SONET OC-768 transmission systems is reported. Both ICs are implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120-GHz f/sub T/ and 100 GHz f/sub max/. The Rx includes a limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector. Input sensitivity for a bit-error rate less than 10/sup -9/ is 40 mV and jitter generation better than 230 fs rms. The IC dissipates 2.4 W from a -3.6-V supply voltage. The Tx integrates a half-rate clock multiplier unit with a 4:1 multiplexer. Measured clock jitter generation is better than 170 fs rms. The IC consumes 2.3 W from a -3.6-V supply voltage.     

2.5Gb/s SDH/SONET通路终结芯片设计

设计了一种2.5Gb/s同步光纤网络SDH/SONET中通路终结处理器芯片.采用双向4路总线流水线结构,77.76MHz的系统时钟,可实时处理2.5Gb/s的SDH/SONET数据,终结处理后输出TUG-3/VTG信号.包括通道告警、信号失效检测、性能监测和通道跟踪等.支持STS-48/STM-16、4路STS-12/STM-4和4路STS-3/STM-1的处理.     

A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONETSTS-192 system

An ultrahigh-speed 8-b multiplexer (MUX) and demultiplexer (DMUX) chip set has been developed for the synchronous optical network (SONET) next-generation optical-fiber communication systems, which will require data bit rates of about 10 Gb/s. These ICs were designed using three novel concepts: a tree-type architecture giving reliable operation, a dynamic divider with a wide operating range, and a 50-Ω on-chip transmission line with high-speed pulse propagation. They were fabricated using a 0.5-μm WN_x-gate GaAs MESFET process. The DMUX and MUX operated at up to 10.4 and 11.4 GHz, respectively, both with an adequate phase margin of more than 230°     

OC-192 transmitter and receiver in standard 0.18-/spl mu/m CMOS

This paper presents the first fully integrated SONET OC-192 transmitter and receiver fabricated in a standard 0.18-/spl mu/m CMOS process. The transmitter consists of an input data register, 16-b-wide first-in-first-out (FIFO) circuit, clock multiplier unit (CMU), and 16:1 multiplexer to give a 10-Gb/s serial output. The receiver integrates an input amplifier for 10-Gb/s data, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. An on-chip LC-type voltage-controlled oscillator (VCO) is employed by both the transmitter and receiver. The chipset operates at multiple data rates (9.95-10.71 Gb/s) with functionality compatible with the multisource agreement (MSA) for 10-Gb transponders. Both chips demonstrate SONET-compliant jitter characteristics. The transmitter 10.66-GHz output clock jitter is 0.065 UI/sub pp/ (unit interval, peak-to-peak) over a 50-kHz-80-MHz bandwidth. The receiver jitter tolerance is more than 0.4 UI/sub pp/ at high frequencies (4-80 MHz). A high level of integration and low-power consumption is achieved by using a standard CMOS process. The transmitter and receiver dissipate a total power of 1.32 W at 1.8 V and are packaged in a plastic ball grid array with a footprint of 11/spl times/11 mm/sup 2/.     

Error-rate measurements on a 1 Gbit/s fibre-optic communications link

Error-rate measurements made on a 1 Gbit/s fibre-optic communications link are described. The link utilises a GaAlAs d.h. injection laser, a 1.6 km single-mode fibre, an avalanche photo-diode and a multiplexer and demultiplexer for four 250 Mbit/s channels. A comparison of the measured results with calculated data using a Gaussian approximation showed good agreement within 2 dB.