Anomalous scaling effect of tungsten/titanium nitride/titanium to silicon electrical contact resistance for subquarter micron microelectronic devices

This paper reports the anomalous scaling effect of tungsten/titanium nitride/titanium to (a) n+ and (b) p+ silicon electrical contact resistance in dynamic random access memory (DRAM) devices, upon post heat treatment following rapid thermal silicidation annealing. The electrical measurements on contacts of sizes ranging from 0.54 μm to 0.18 μm reveal that the increase in resistance becomes larger as the contact size decreases. Transmission electron microscopy (TEM) results show that the silicide film agglomeration proceeds more severely as the contact size decreases. To explain the size-dependent degradation of the contact resistance, numerical simulation of the shape evolution of the silicide film is performed. The results show that the poor film coverage, especially at the edge, accelerates the reduction rate in contact area.     

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant

Electrical and SEM analysis of gate-silicided (GS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism changes from source-to-drain filamentation to drain-to-substrate short when a p-type ESD implant (ED) is used. Simulations show that the reason for change in failure mode is the different current and temperature distribution when the device is operated in bipolar mode due to the presence of ED. The size of the drain silicide blocking can be reduced from 3 to 0.75 μm by the use of ED while keeeping the same ESD failure current with the corresponding area saving benefit. When the ED implant extends under the drain contacts, the on-resistance (Ron) of the device can be reduced by 50% with respect to a design where ED is not located under the contacts.     

ESD电热模拟分析

在分析ESD失效机制的基础上,介绍了目前热击穿的研究情况,指出器件失效前所承受的功率与时间的关系对于研究热击穿的重要性;然后介绍了几个关于失效功率的热模型,分析了相关ESD模拟软件工具,提出一套有效的ESD模拟方法.     

液晶屏幕抗静电分析与对策

液晶屏幕越来越多地应用在信息技术设备当中,但是液晶屏幕防静电技术却一直困扰着很多工程师.通过分析液晶屏幕显示原理,结合静电场理论,分析静电放电(ESD)对液晶屏幕的影响,并提供整改实例,简要介绍此类问题的处理方法.     

Electrochemical mechanism of layout-dependent corrosion of tungsten in contact plugs

The investigation elucidates electrochemical effect on tungsten (W) contact plugs and proposes front-end-of-the-line semiconductor manufacture processes that are responsible for corrosion involving source/drain implants, rapid thermal anneal (RTA) and nickel silicide (Ni_xSi_x). W-filled contacts are commonly used in submicron and even nanometer CMOS technology, and the integrity of W contact plugs becomes increasingly critical as transistors continue to shrink. Incomplete W plugs with a recess on the tops of the contacts were observed in N+/n-well locations following W chemical mechanical polishing (WCMP). This phenomenon arises from anodic corrosion since the under-layer P+/p-well and N+/n-well form a PN junction structure, which has built-in potential and promotes the movement of photo-generated electrons during WCMP. The mechanism of the electrochemical effect is elucidated, and a series of experiments indicates a thin Ni_xSi_x layer, a heavy dosage of source/drain implants and a high RTA temperature promote the formation of corrosion defects.     

Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up

Current flow uniformity during ESD induced latch-up event is investigated in multi-finger LDMOS clamps and SCR ESD protection devices fabricated in a 0.6 μm high voltage CMOS process. Current flow, excess free carrier and hot spot distribution are analyzed by transient interferometric mapping technique combined with a latch-up pulse system consisting of a solid state pulser and a clear pulse unit. During latch-up, the current in the LDMOS clamps flows just in a single spot and the failure position is random and independent on device type. The position of the failure site correlates with the trigger position of the device. The SCRs exhibit pulse-to-pulse instabilities in the current flow.     

一种电路的静态损伤机理分析

介绍了电路静态电荷放电的三种模型,并对组件充电模型进行了详细介绍。对电路的失效现象进行分析,失效原因在于电路在组件充电模型下抗静态电荷损伤能力较弱,并提出了新的防电路静态损伤结构来解决组件充电模型下电路防静电能力不足的问题。     

电子产品静电放电失效分析与对策

介绍了静电放电的两种耦合路径,通过实际案例,分析了测试过程中遇到的静电放电原因,并分别采取了接地、隔离、提供能量泄放通道等整改措施.整改后的产品都通过了相关的测试.     

Laser interferometric method for ns-time scale thermal mapping of Smart Power ESD protection devices during ESD stress

A backside heterodyne interferometric technique is presented to study thermal effects in smart-power electrostatic discharge (ESD) protection devices during the ESD stress. The temperature increase in the device active area causes an increase in the silicon refractive index (thermo-optical effect) which is monitored by the time-resolved measurements of optical phase changes. Thermal dynamics and spatial temperature distribution in different types of npn transistor structures biased in the avalanche multiplication or snapback regime are studied with nanosecond time and micrometer spatial resolution. The activity and inactivity of the bipolar transistor action is indicated by the dominant signal arising from the emitter or base region, respectively. Hot spots have been found at the edges of the structures and attributed to the current crowding effect in the emitter.     

Ruthenium and tungsten as contact materials in hermetically plastic sealed telecom- and signal-relays

Palladium is the most frequently used contact material for telecommunication and signal relays. Good contact resistance stability and material transfer characteristics make it the most often used. The strong variation of the palladium price in recent years has made it necessary to look for alternatives. The development of gas-tight plastic sealed relay housings, which keep the gas filling inside the relay for a long time, e.g., more than 10 years for nitrogen and more than 100 years for sulfur-hexafluoride, allows nonprecious metal contact materials to be used, as an inert atmosphere can be kept for the entire life of the relay. Tests were performed with gold covered tungsten and ruthenium contacts mounted in a standard telecom relay filled with N/sub 2/ or SF/sub 6/. Although the contact resistance was always measured with dry circuit conditions applied, no relevant increase was observed during all electrical endurance tests. The ruthenium as well as the tungsten layer with a thickness of only 5 /spl mu/m withstood endurance tests at maximum loads at 30 W. As only minimum contact erosion and material transfer occurred, no contact sticking or bridging was observed. Overall the switching performance of tungsten and ruthenium is similar to PdRu10. As PdRu10 has superior performance especially when operating in an SF/sub 6/ atmosphere, the properties of Ru and W in N/sub 2/ as well as in SF/sub 6/ are at least comparable with all contact materials in current use. Gas-tight plastic sealed relay housings offer the advantages of hermetically sealed housings at an affordable cost.     

LDMOS器件ESD防护特性分析与优化设计

LDMOS器件具有高输出功率、高增益、高线性、良好的热稳定性等优点,广泛应用于功率集成电路中,但在ESD防护过程中易发生双回滞而降低ESD鲁棒性。基于0.25μm Bipolar-CMOSDMOS工艺,分析了LDMOS器件峰值电场的转移是发生双回滞现象并引起弱鲁棒性的主要原因,提出阳极用P+替代N+的版图改进方法。TLP测试制备的LDMOS器件显示,器件漏电流稳定维持在10-8A量级,二次失效电流大于9 A。结果表明,抑制的双回滞能有效增强鲁棒性,使其适用于高压功率集成电路的ESD防护。     

ESD保护低噪声放大器的分析与设计

针对封装和ESD寄生对源极电感反馈结构低噪声放大器的影响,进行了详细的理论分析。在已发表文献的基础上,加入对ESD寄生引起的输入匹配网络改变的考虑,给出了新的噪声系数公式。根据分析结果,提出设计时的考虑。采用0.18μm CMOS工艺,设计了一款GPS L1波段的单端低噪声放大器。测试结果显示,电路增益达到18dB,噪声系数为2.2dB;在1.8V电压下,电流消耗为4.5mA。     

几个ESD标准版本的差异分析

介绍《GB/T17626.2-2006电磁兼容试验和测量技术静电放电抗扰度试验》与《GB/T17626.2-1998》版及〈IEC61000-4-2：2008〉版的主要差异和分析,可供EMC试验工程师参考。     

Thermal and free carrier concentration mapping during ESD event in smart Power ESD protection devices using an improved laser interferometric technique

Spatial distribution of temperature and free-carrier concentration during high-current stress is studied in smart power electrostatic discharge (ESD) protection devices using a backside laser interferometric technique. The method is based on detecting changes in the refractive index of silicon due to thermo-optical and plasma-optical effects. We use a modified version of a heterodyne interferometer, where the reference beam is reflected from an external mirror outside the sample chip, which allows one to perform measurements without any restriction to the size of the scanning area. We have found two pronounced heat dissipating regions due to a vertical and a lateral current flow path in the device. In addition, two regions with increased current density due to carrier injection related to the two current paths have been found. These temperature and carrier concentration distributions found by the experiment agree very well with the results of 2D device simulation.     

浅谈电子制造过程中的静电及静电防护

静电释放（ESD）就是一定数量的电荷从一个物体（例如人体）传送到另一个物体（例如芯片）的过程。这个过程能导致在极短的时间内有一个非常高的电流通过芯片,35％以上的芯片损坏都可以归咎于此。因此,在电子制造行业里保护芯片免受静电释放的损害是非常重要的。实际上,很多企业在各种不同电子应用中都遇到了如何应对急速增长的静电防护需求的问题。文章针对ESD机制和防护做了一个较全面的介绍,包括ESD原理、电流产生、危害、防静电工艺要求等。     

深亚微米GGNMOS器件ESD鲁棒性的优化与模拟

基于单指条栅接地N型场效应晶体管(GGNMOS)在静电放电(ESD)时的物理级建模方法,仿真分析了版图参数和工艺参数对器件ESD鲁棒性的影响。提出了一种可提高器件ESD保护性能的优化设计,即硅化扩散工艺下带有N阱的多指条GGNMOS结构。对单指条器件模型进行修正,得到的多指条模型能预估不同工艺条件下所需的N阱长度,以满足开启电压V_t1小于热击穿电压V_t2的设计规则。由仿真结果可知,对于一个0.35 μm工艺下的10指条GGNMOS,通过减小栅极长度(L)、提高衬底掺杂浓度(NBC)和漏极掺杂浓度(NE),以及从修正模型中得到合适的N阱长度,均可以增强器件的ESD鲁棒性。     

Frequency-Domain Measurement Method for the Analysis of ESD Generators and Coupling

A method for analyzing electrostatic discharge (ESD) generators and coupling to equipment under test in the frequency domain is proposed. In ESD generators, the pulses are excited by the voltage collapse across relay contacts. The voltage collapse is replaced by one port of a vector network analyer (VNA). All the discrete and structural elements that form the ESD current pulse and the transient fields are excited by the VNA as if they were excited by the voltage collapse. In such a way, the method allows analyzing the current and field-driven linear coupling without having to discharge an ESD generator, eliminating the risk to the circuit and allowing the use of the wider dynamic range of a network analyzer relative to a real-time oscilloscope. The method is applicable to other voltage-collapse-driven tests, such as electrical fast transient, ultrawideband susceptibility testing but requires a linear coupling path.     

Layered and homogeneous films of aluminum and aluminum/silicon with titanium and tungsten for multilevel interconnects

Layered structures and homogeneous alloy films synthesized by sputter deposition were investigated for use in a VLSI multilevel interconnect technology. Major areas studied include hillock formation, resistivity before and after annealing, film composition and structure, reproducibility, interlevel shorts, and dry etching. It has been demonstrated in this work that aluminum alloyed with silicon and titanium and layered with titanium offers advantages over current technological materials for interconnections in integrated circuits. Measurements of surface roughness and electrical shorts between two levels of metal showed that the hillock densities in the films are significantly reduced when small amounts (one to three atomic percent) of titanium and silicon are present. The resistivity of such homogeneous films, however, is 4.5 to 5.5 µΩ.cm, which is higher than standard metallization alloys. When Al/Si was layered with Ti, no hillocks were observed and the resistivity of the composite films was comparable to standard metallization alloys.     

Gate Grounded NMOS器件的ESD性能分析

文章基于0.18μm CMOS工艺制程的1.8V NMOS器件,从工艺的角度并用TLP测试系统对栅极接地的NMOS(GGNMOS)ESD器件进行比较分析.介绍了SAB和ESD注入对GGNMOS的性能影响,影响GGNMOS ESD性能的瓶颈是均匀开启性.在GGNMOS版图等其他特征参数最优的前提下,采用SAB能改善其均匀...     

ESD与短脉冲EOS失效的微观形态分析及验证

静电放电(ESD)和过电应力(EOS)是引起芯片现场失效的最主要原因,这两种相似的失效模式使得对它们的失效机理的判断十分困难,尤其是短EOS脉冲作用时间只有几毫秒,造成的损坏与ESD损坏很相似。因此,借助扫描电子显微镜(SEM)和聚焦离子束(FIB)等成像仪器以及芯片去层处理技术分析这两种失效机理的差别非常重要。通过实例分析这两种失效的机理及微观差别,从理论角度解释ESD和EOS的失效机理,分析这两种失效在发生背景、失效位置、损坏深度和失效路径方面的差异,同时对这两种失效进行模拟验证。这种通过失效微观形态进行研究的方法,可以实现失效机理的甄别,对于提高ESD防护等级和EOS防护能力有着重要的参考作用。