共查询到19条相似文献,搜索用时 62 毫秒
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C波段CMOS射频前端电路设计与实现 总被引:1,自引:0,他引:1
设计了一款工作在C波段(4.2 GHz)的CMOS射频前端电路,电路包括低噪声放大器和Gilbert型有源双平衡混频器.其中低噪声放大器采用共源和共栅放大器方式,实现了单端输入到差分输出的变换;而混频器的输出端采用电感负载形式.电路采用SMIC 0.18μmRF工艺实现,测试结果表明,混频器的输出频率约为700 MHz,电路的功率增益为24 dB,单边带噪声指数为8 dB,在1.8 V工作电压下,电路总功耗为36 mW. 相似文献
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设计了一款应用在433MHz ASK接收机中的射频前端电路。在考虑了封装以及ESD保护电路的寄生效应的同时,从噪声、匹配、增益和线性度等方面详细讨论了低噪声放大器和下混频器的电路设计。采用0.18μm CMOS工艺,在1.8V的电源电压下射频前端电路消耗电流10.09 mA。主要的测试结果如下:低噪声放大器的噪声系数、增益、输入P1dB压缩点分别为1.35 dB、17.43 dB、-8.90dBm;下混频器的噪声系数、电压增益、输入P1dB压缩点分别为7.57dB、10.35dB、-4.83dBm。 相似文献
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设计了一款工作在2.4GHz的可变增益CMOS低噪声放大器,电路采用HJKJ0.18μm CMOS工艺实现。测试结果表明,最高增益为11.5dB,此时电路的噪声系数小于3dB,增益变化范围为0~11.5dB。在1.8V电压下,电路工作电流为3mA。 相似文献
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我们利用0.18μm CM O S工艺设计了低噪声放大器。所有电感采用片上螺旋电感,全集成在单个芯片上,并实现片内50Ω匹配。本次电路设计分析采用ADS仿真软件,电源电压1V,工作电流8mA,增益为15.4dB,噪声系数2.7dB,线性度指标IIP 3为-0.6dB。结论是CM O S工艺在工艺和模型方面的改进,使得CM O S RF电路设计更为精确,可集成度更高。 相似文献
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铁宏安 《固体电子学研究与进展》2009,29(3)
采用0.18μm1.8V mixed CMOS工艺设计并实现了一种应用于GPS接收机的CMOS低噪声放大器,采用片内螺旋电感实现输入匹配和单片集成。测试结果表明在1.575GHz时,工作电流8mA,增益20dB,噪声系数小于1.7dB,IIP3为-10dBm。 相似文献
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E. Garcia-Moreno Author Vitae K. Suenaga Author VitaeAuthor Vitae S. Bota Author VitaeAuthor Vitae E. Isern Author Vitae 《Integration, the VLSI Journal》2009,42(1):95-102
In this paper, we present two built-in self-test strategies for the down-converter stage in a GSM receiver. These strategies are based on the prediction of its performance parameters from measurements in test mode. By reusing some receiver blocks as part of the test set-up, the circuitry overhead is kept small. The first strategy uses the local oscillator (LO) signal as the only test stimuli. The second strategy uses additional test circuitry, a generator, and an auxiliary mixer. Prediction accuracies are similar in both strategies, but the test observables in the second one are easier to be obtained. 相似文献
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基于0.18 μm CMOS工艺,设计了一种面向低速率低功耗应用的2.4 GHz射频前端电路,包含2个单刀双掷开关、1个功率放大器和1个低噪声放大器。采用栅衬浮动电压偏置技术对传统单刀双掷开关进行了改进,以提高其线性度;功率放大器采用两级放大结构,对全集成的低噪声放大器进行了噪声优化;集成了输入输出匹配网络,采用了到地电感,以提高输入输出端的ESD性能。在接收模式时,电路的静态电流为10.7 mA,增益为11.7 dB,IIP3为2.1 dBm,噪声系数为3.4 dB。在发射模式时,电路的静态电流为17.4 mA,功率增益为17.7 dB,输出P1dB为20 dBm,饱和功率为21.4 dBm,最大PAE为23.8%,在输出功率为20 dBm时的频谱满足802.15.4协议要求。 相似文献
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Kwok-kei Kan Dongsheng Ma Kin-chung Mak Howard C. Luong 《Analog Integrated Circuits and Signal Processing》2000,24(2):101-111
A CMOS mixer topology capable of both downconversion and upconversion mixing for use in integrated wireless transceivers is presented. The mixing is based on two cross-coupled differential pairs as commutators with two source-followers as current modulators. Independence of the input and output bandwidths allows this topology to be optimized separately for either downconversion or upconversion mixer. The prototypes of both upconversion and downconversion mixers, optimized for linearity and realized in 0.8 m CMOS technology, have been demonstrated to fully operate at 1 GHz with good linearity and low power consumption. In addition, another mixer, optimized for noise figure and realized in 0.5 m CMOS technology, has been designed to achieve a NF of around 12 dB. 相似文献
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通过一个符合性能指标的,用于射频接收系统的CMOS低噪声放大性能的设计,讨论了深亚微米MOSFET的噪声情况,并在满足增旋和功耗的前提下,对低噪声放大噪声性能进行分析和优化,该LNA工作在2.5GHz电源电压,直流功耗为25mW,能够提供19dB的增益(S21),而噪声系数仅为2.5dB,同时输入匹配良好,S11为-45dB,整个电路只采用了一个片外电感使电路保持谐振,此设计结果证明CMOS工艺在射频集成电路设计领域具有可观的潜力。 相似文献
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P. J. Sullivan B. A. Xavier W. H. Ku 《Analog Integrated Circuits and Signal Processing》1999,19(2):181-188
A CMOS doubly balanced mixer circuit is implemented with a source follower input and a cross coupled mixing quad. The circuit employs an all N-channel configuration and is suitable for high frequency applications. As a down-converter with an RF input of 2.0 GHz and an IF output of 200 MHz, the mixer demonstrates 9 dB of conversion loss with a corresponding input referred third order intercept of 0 dBm. As an up-converter with an IF input frequency of 400 MHz and an RF output of 2.4 GHz, the mixer demonstrates 14 dB of conversion loss. 相似文献
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Payam Heydari 《Analog Integrated Circuits and Signal Processing》2006,48(3):199-209
An analysis of high-frequency noise in RF active CMOS mixers including single-balanced and double-balanced architectures is
presented. The analysis investigates the contribution of non-white gate-induced noise to the output noise power as well as
the spot noise figure (NF) of the RF CMOS mixer. It accounts for the non-zero correlation between the gate-induced noise and
the channel’s thermal noise. The noise contribution of the RF transconductor and the switching pair to the output noise power
is studied. Experimental results verify the accuracy of the analytical model.
Payam Heydari (S’98–M’00) received the B.S. and M.S. degrees in electrical engineering from the Sharif University of Technology, in 1992,
1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California, in
2001.
During the summer of 1997, he was with Bell-Labs, Lucent Technologies, where he worked on noise analysis in deep submicrometer
very large-scale integrated (VLSI) circuits. During the summer of 1998, he was with IBM T. J. Watson Research Center, Yorktown
Heights, NY, where he worked on gradient-based optimization and sensitivity analysis of custom-integrated circuits. Since
August 2001, he has been an Assistant Professor of Electrical Engineering at the University of California, Irvine, where his
research interest is the design of high-speed analog, RF, and mixed-signal integrated circuits.
Dr. Heydari has received the 2005 National Science Foundation (NSF) CAREER Award, the 2005 IEEE Circuits and Systems Society
Darlington Award, the 2005 Henry Samueli School of Engineering Teaching Excellence Award, the Best Paper Award at the 2000
IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Mention Award from the Department of EE-Systems
at the University of Southern California, and the 2001 Technical Excellence Award in the area of Electrical Engineering from
the Association of Professors and Scholars of Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty
at the EECS Department of the University of California, Irvine. His name was included in the 2006 Who’s Who in America.
Dr. Heydari Professor Heydari has been the Associate Editor of IEEE TRANS. ON CIRCUITS AND SYSTEMS, I, since 2006. He currently
serves on the Technical Program Committees of International Symposium on Low-Power Electronics and Design (ISLPED), International
Symposium on Quality Electronic Design (ISQED), and the Local Arrangement Chair of the ISLPED conference. He was the Student
Design Contest Judge for the DAC/ISSCC Design Contest Award in 2003, the Technical Program Committee member of the IEEE Design
and Test in Europe (DATE) from 2003 to 2004, and International Symposium on Physical Design (ISPD) in 2003. 相似文献