纳米尺度多晶硅微结构刻蚀研究

以HBr作为刻蚀气体,采用ICP金属刻蚀系统对气体流量、刻蚀压力、离子源功率、偏压功率等工艺参数与刻蚀速率、刻蚀选择比和侧壁垂直度的对应关系进行了大量工艺实验。借助理论分析和工艺条件的优化,开发出一套可满足制备侧壁垂直度的纳米尺度多晶硅密排线结构的优化刻蚀工艺技术。实验结果表明:当采用900 W的离子源功率、11 W的偏压功率、25 cm3/min流量的HBr气体和3 mTorr(1 mTorr=0.133 3 Pa)刻蚀压力的工艺条件时,多晶硅与二氧化硅的刻蚀选择比大于100∶1;在保持离子源功率、偏压功率、气体流量不变的条件下,单纯提高反应腔工艺压力则会大幅提高上述选择比值,同时损失多晶硅和二氧化硅的刻蚀均匀性;HBr气体流量的变化在上述功率及反应腔工艺压力的工艺范围内,对多晶硅与二氧化硅的刻蚀选择比和多晶硅刻蚀的形貌特征均无显著影响。采用上述优化的刻蚀工艺条件,配合纳米电子束光刻技术成功得到多晶硅纳米尺度微结构,其最小线宽为40 nm。     

ICP腔体压力对直流偏压的影响

基于GaAs器件干法刻蚀工艺,介绍感应耦合等离子(ICP)的刻蚀原理,以Cl2和BCl3为刻蚀气体,研究分析了在GaAs表面刻蚀工艺中不同的腔体压力下设备直流偏压的变化情况.发现在各种不同的功率下都存在一个特定的腔体压力,当低于该腔体压力时直流偏压会随腔体压力的增大而增加,当高于该腔体压力后直流偏压会随着腔体压力的增加而缓慢减小.讨论了产生这种现象的原因,揭示了其中的物理机理,以该方法作为参考,通过一组对比实验在工艺中得到验证,给出了GaAs刻蚀的工艺条件,为刻蚀工艺条件的优化提供了一个参考.     

ICP刻蚀GaN侧壁倾角以及刻蚀速率的控制

深入研究了Cl2基气体电感耦合等离子体(ICP)刻蚀系统对于GaN材料侧壁倾角的控制以及刻蚀速率的影响。通过调整ICP离子源功率、射频功率、气体流量、腔室压力等参数,经实验验证,实现了从23°～83°侧壁倾角的大范围工艺控制,为GaN基器件工艺提供了有益指导。     

ICP等离子体刻蚀系统射频偏压的实验研究

对于上下电极双射频源的电感耦合(ICP)等离子体刻蚀设备的关键工艺参数--下电极射频偏压的变化特性进行了实验与物理定性分析.实验以氧气作为反应气体,采用可满足300mm硅晶片刻蚀的ICP刻蚀设备的射频系统进行实验数据测定.结果表明,下电极射频偏压与其他工艺参数在可适用的工艺窗口中(改变上下电极功率和气体压力)不再是平常认为的简单的比例关系,而是随着条件的改变,对应的趋势比例关系会发生转折性变化,这种变化在高上电极射频、低下电极射频功率和低气压的条件下很容易发生.     

ICP等离子体刻蚀系统射频偏压的实验研究

对于上下电极双射频源的电感耦合(ICP)等离子体刻蚀设备的关键工艺参数--下电极射频偏压的变化特性进行了实验与物理定性分析.实验以氧气作为反应气体,采用可满足300mm硅晶片刻蚀的ICP刻蚀设备的射频系统进行实验数据测定.结果表明,下电极射频偏压与其他工艺参数在可适用的工艺窗口中(改变上下电极功率和气体压力)不再是平常认为的简单的比例关系,而是随着条件的改变,对应的趋势比例关系会发生转折性变化,这种变化在高上电极射频、低下电极射频功率和低气压的条件下很容易发生.     

高均匀性高选择性的多晶硅刻蚀工艺

作者采用HCl和HBr作为刻蚀气体，在Tegal1611设备上刻蚀Poly－Si，研究了工艺条件，如压力、功率等对工艺结果的影响，得到了相当好的工艺结果，并成功地应用于125mm晶片MOS电路的大生产中。     

二氧化硅的反应离子刻蚀

对电子束曝光和反应离子刻蚀(RIE)进行了研究。刻蚀使用JR-2B型溅射-刻蚀机,分别采用100W、150W、200W、250W、300W的功率,对SiO2进行了刻蚀,反应气为:CHF3,对影响刻蚀的射频功率以及压力、气体流量等工艺参数作了调整,得出了刻蚀速率与射频功率和压力之间、气体流量的关系曲线。实验结果表明:随着射频功率、压力的增大,刻蚀速率不断加快,在某一值上达到最大值。再继续增加射频功率、压力,刻蚀速率反而会下降。随着气体流量的增加,刻蚀速度不断降低。     

GaN电感耦合等离子体刻蚀的优化和损伤分析

通过分别改变电感耦合等离子体(ICP)刻蚀过程中的ICP功率和DC偏压,对ICP刻蚀GaN材料的工艺条件和损伤情况进行了系统的研究。刻蚀后表面的损伤和形貌通过扫描电子显微镜(SEM)、原子力显微镜(AFM)、电子能谱(EDS)、荧光光谱(PL)等技术进行表征和分析。实验结果表明,刻蚀速率随ICP功率和DC偏压的增加而增加;刻蚀损伤与DC偏压成正比,而与ICP功率的关系较为复杂。实验中观测到刻蚀后GaN样品的荧光光谱带边发射峰和黄带发射峰的强度均有明显下降,这意味着刻蚀产生的缺陷中存在非辐射复合中心,并且该非辐射复合中心的密度与DC偏压成正比。为了兼顾高刻蚀速率和低刻蚀损伤,建议使用高ICP功率(450 W)和低DC偏压(300 V)进行ICP刻蚀。     

利用氟化气体和氧气的混和物进行SiC薄膜的反应离子刻蚀

本文研究了在ＳＦ６，ＣＢｒＦ３和ＣＨＦ３与氧相混合的几种氟化气体等离子体中，ＳｉＣ薄膜反应离子刻蚀（ＲＩＥ）的深度。通过监测射频等离子体的光发射谱及产生等离子体的直流偏压来研究刻蚀机理，为了更精确地定量分析刻蚀工艺，使用氩光能测定技术使等离子发射强度转换为相应的等离子物质浓度。为获得选择性的ＳｉＣ－Ｓｉ刻蚀及ＳｉＣ薄膜的各向异性图形，对等离子体条件，如气体混合物的构成，压力和功率进行了研究。首次采     

相变材料等离子体刻蚀的研究进展

首先综述了相变材料等离子体刻蚀技术的研究进展,然后讨论了影响相变材料等离子体刻蚀的主要工艺参数,如线圈功率、腔体气压、偏压、刻蚀气体及气体比例等,进而解释了工艺参数与刻蚀结果的依赖关系。同时采用多种分析手段,对相变材料在等离子体刻蚀工艺中产生的刻蚀损伤进行了分类和表征,并基于该分析结果提出了工艺优化方案。最后总结了相变材料等离子体刻蚀技术的反应机理,相变材料的刻蚀是自发反应与离子辅助化学反应相结合的过程,同时物理溅射与低挥发性产物的离子激发脱附也起着重要的辅助作用。     

Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

Virtual Metrology Modeling for Plasma Etch Operations

The objective of this paper is to present the utilization of information produced during plasma etching for the prediction of etch bias. A plasma etching process typically relies on the concentration of electrically activated chemical species in a reaction chambers over time, depending on chamber pressure, gas flow rate, power level, and other chamber and wafer properties. Plasma properties, as well as equipment factors, are complex and vary over time. In this paper, we will use various statistical techniques to address challenges due to the nature of plasma data: high dimensionality, colinearity, parameter interactions and nonlinearities, variation of data structure due to equipment condition changing over time, etc. The emphasis will be data integrity, variable selection, accommodation for process dynamics, and model-building methods. Different techniques will be evaluated with an industrial dataset.      

基于高深宽比Si干法刻蚀参数优化

为满足体硅MEMS制造工艺进一步发展的需要,对电感耦合等离子体(ICP)刻蚀工艺参数进行了深入分析,着重分析了平板功率对Si干法刻蚀的影响。通过对Si干法刻蚀的主要工艺参数进行正交试验,得出了一组较为理想的刻蚀工艺参数:刻蚀气体SF6和保护气体C4F8的流量均为13cm3·min-1,在一个周期内通入刻蚀气体SF6的时间为4s,通入钝化气体C4F8的时间为3s;线圈功率为400W,平板功率为110W。利用这组优化的工艺参数进行Si的干法刻蚀,所得到的微结构的深宽比将大于20∶1,同时侧壁垂直度能够很好地控制在90°±1°。     

等离子体刻蚀工艺中的OES监控技术

采用光学发射光谱(OES)原位检测技术,对等离子体刻蚀机中的等离子体状态进行实时监控,讨论了其在故障诊断、分类、刻蚀终点的判断及控制方面的应用。实验平台为在新研发的高密度等离子体刻蚀机,采用化学气体HBr/Cl₂为刻蚀气体进行多晶硅刻蚀工艺实验,实验过程中所采集的OES数据通过PCA法进行分析,得到与刻蚀过程相关的特征谱线。实验结果表明：OES技术适合于深亚微米等离子体刻蚀工艺过程的终点检测及故障诊断。最后就OES技术未来发展面临的挑战进行了讨论。     

Characterization of Via Etching in CHF3/CF4 Magnetically Enhanced Reactive Ion Etching Using Neural Networks

This study characterizes an oxide etching process in a magnetically enhanced reactive ion etching (MERIE) reactor with a CHF3/CF4 gas chemistry. We use a statistical 2^4‐1 experimental design plus one center point to characterize the relationships between the process factors and etch responses. The factors that we varied in the design include RF power, pressure, and gas composition, and the modeled etch responses were the etch rate, etch selectivity to TiN, and uniformity. The developed models produced 3D response plots. Etching of SiO₂ mainly depends on F density and ion bombardment. SiO₂ etch selectivity to TiN sensitively depends on the F density in the plasma and the effects of ion bombardment. The process conditions for a high etch selectivity are a 0.3 to 0.5 CF₄ flow ratio and a –600 V to –650 V DC bias voltage according to the process pressure in our experiment. Etching uniformity was improved with an increase in the CF4 flow ratio in the gas mixture, an increase in the source power, and a higher pressure. Our characterization of via etching in a CHF₃/CF₄ MERIE using neural networks was successful, economical, and effective. The results provide highly valuable information about etching mechanisms and optimum etching conditions.     

Hybrid dry-wet chemical etching process for via holes for galliumarsenide MMIC manufacturing

Through the wafer via-hole connections for monolithic microwave integrated circuits (MMIC) manufacturing have been developed by combining reactive ion etching (RIE) and wet chemical spray etching processes for 100-μm-thick gallium arsenide wafers. The dry process is based on the use of SiCl₄-BCl₃-Cl₂ and BCl₃-Cl₂ gas mixtures at room temperature is a reactive ion etcher. The etching parameters are optimized for anisotropic etching, initially, followed by slightly isotropic etching. To remove the residual `lip' and surface roughness, following reactive ion etching, a dynamic wet chemical spray etching based on H₃PO₄-H₂O₂-H₂O at 45°C is used. The combined dry-wet etching approach is used to fabricate <120-μm diameter via-holes in 100-μm-thick GaAs substrates with a wider process latitude. With this process, the authors have achieved >95 percent yield across 3-in wafers. Metallized via-hole contacts to power FET chips show a contact resistance <20 mΩ per via for 5-μ-thick selective gold plating     

HBr反应离子刻蚀硅深槽

对ＨＢｒ反应离子刻蚀硅和ＳｉＯ２进行了实验研究。介绍了ＨＢｒ等离子体的刻蚀特性，讨论了ＨＢｒ反应离子刻蚀硅的刻蚀机理，研究了ＨＢｒ中微量氧、碳对ＨＢｒＲＩＥ刻蚀过程的影响。实验表明，ＨＢｒ是一种刻蚀硅深槽理想的含原子溴反应气体。采用ＨＢｒＲＩＥ，可获得高选择比（对Ｓｉ／ＳｉＯ２）和良好的各向异性。