A new semi-flat architecture for high speed and reduced area CORDIC chip

In this contribution we present a new CORDIC architecture called ‘semi-flat’ which reduces considerably the latency time and the amount of hardware. In our semi-flat architecture the first rotations are executed with an unfolded scheme but the remaining iterations are flattened using a fast redundant addition tree. Detailed comparisons with other major contributions show that our semi-flat redundant CORDIC is 30% faster and occupy 39% less silicon area.     

芯片贴装用银浆料的热物理与力学性能

针对集成电路半导体芯片贴装,替代金-硅共熔焊或导电胶类粘结剂,研制了一种由银粉、玻璃粉和有机载体组成的低温烧结型银基浆料,其烧结温度峰值为430℃。研究了浆料的成分配比、工艺及其芯片贴装烧结工艺对浆料烧结体的微观组织、αL、λ、芯片组装的剪切力和热循环对芯片剪切力的影响规律。结果表明,当ζ(银粉:玻璃粉)=7:3,ζ(固体混合粉末:有机载体)=8:2时,芯片贴装后的综合性能最佳,冷热循环500次后其剪切力仅下降15%。     

Temperature measurements and thermal modeling of high power IGBT multichip modules for reliability investigations in traction applications

To study the failure mechanisms induced on high power IGBT multichip modules by thermal cycling stress in traction environment, a good knowledge of the temperature distribution and variations on the chips and in the interfaces between the different layers of the packaging is necessary. This paper presents a methodology for contact temperature measurements on chips surface in power cycling conditions and a fast 3D thermal simulation tool for multilayered hybrid or monolithic circuits. The results of static and dynamic thermal simulation of a 1200A–3300V IGBT module are given and compared with the contact temperature measurements results. The investigation has been done within the RAPSDRA (Reliability of Advanced High Power Semiconductor Device for Traction Applications) European project.     

A Fast Autonomous Healing Magnetic Elastomer for Instantly Recoverable,Modularly Programmable,and Thermorecyclable Soft Robots

Intrinsically self-healing stretchable polymers have been intensively explored for soft robotic applications due to their mechanical compliance and damage resilience. However, their prevalent use in real-world robotic applications is currently hindered by various limitations such as low mechanical strength, long healing time, and external energy input requirements. Here, a self-healing supramolecular magnetic elastomer (SHSME), featuring a hierarchical dynamic polymer network with abundant reversible bonds, is introduced. The SHSME exhibits high mechanical strength (Young's modulus of 1.2 MPa, similar to silicone rubber) and fast self-healing capability (300% stretch strain after 5 s autonomous repair at ambient temperature). A few SHSME-based robotic demonstrations, namely, rapid amphibious function recovery, modular-assembling-prototyping soft robots with complex geometries and diverse functionalities, as well as a dismembering–navigation–assembly strategy for robotic tasking in confined spaces are showcased. Notably, the SHSME framework supports circular material design, as it is thermoreformable for recycling, demonstrates autorepair for extended lifespan, and is modularizable for customized constructs and functions.     

DS-CDMA chip waveform design for minimal interference underbandwidth, phase, and envelope constraints

This paper investigates the effect of chip waveform shaping on the error performance, bandwidth confinement, phase continuity, and envelope uniformity in direct-sequence code-division multiple-access communication systems employing offset quadrature modulation formats. An optimal design methodology is developed for the problem of minimizing the multiple-access interference power under various desirable signal constraints, including limited 99% and 99.9% power bandwidth occupancies, continuous signal phase, and near-constant envelope. The methodology is based on the use of prolate spheroidal wave functions to obtain a reduced-dimension discrete constrained optimization problem formulation. Numerous design examples are discussed to compare the performance achieved by the optimally-designed chip waveforms with other conventional schemes, such as offset quadrature phase-shift keying, minimum-shift keying (MSK), sinusoidal frequency-shift keying (SFSK), and time-domain raised-cosine pulses. In general, it is found that while the optimized chip pulses achieved substantial gains when no envelope constraints were imposed, these gains vanish when a low envelope fluctuation constraint was introduced. In particular, it is also shown that MSK is quasi-optimal with regard to the 99% bandwidth measure, while the raised-cosine pulse is equally good with both the 99% and 99.9% measures, but at the expense of some envelope variation. On the other hand, SFSK is quasi-optimal with regard to the 99.9% bandwidth occupancy, among the class of constant-to-low envelope variation pulses     

TESTCHIP: a chip for weighted random pattern generation,evaluation, and test control

In self-testable circuits, additional hardware is incorporated for generating test patterns and evaluating test responses. A built-off test strategy is presented which moves the additional hardware to a programmable extra chip. This is a low-cost test strategy in three ways: (1) the use of random patterns eliminates the expensive test-pattern computation; (2) a microcomputer and an ASIC (application-specific IC) replace the expensive automatic test equipment; and (3) the design for testability overhead is minimized. The presented ASIC generates random patterns, applies them to a circuit under test, and evaluates the test responses by signature analysis. It contains a hardware structure that can produce weighted random patterns corresponding to multiple programmable distributions. These patterns give a high fault coverage and allow short test lengths. A wide range of circuits can be tested as the only requirement is a scan path and no other test structures have to be built in     

No-flow underfill process modeling and analysis for low cost, high throughput flip chip assembly

A new defect in which a chip "floats" over the board surface after chip placement is appearing in the low-cost, high-throughput flip chip on board (FCOB) assembly that is based on no-flow underfill. This defect has the potential to significantly lower process yield when process variables are not properly controlled. In fact, it was found that much of the yield loss observed post reflow is attributable to "chip floating." A process model has been developed that will allow an understanding of the underlying physics of the floating phenomena and identification of process variables so that this process defect can be eliminated. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was specially designed so that chip floating over the board can be easily detected. To validate the model, the effects of the critical process variables on chip floating were investigated by a series of experiments, and the results were compared to the theoretical model's predictions.     

Characteristics and reliability of fast-flow, snap-cure, and reworkable underfills for solder bumped flip chip on low-cost substrates

In this study, the fast-flow, fast-cure, and reworkable underfill materials from two different vendors are considered. Emphasis is placed on the determination of the curing conditions such as temperature and time, and the material properties such as the thermal coefficient of expansion (TCE), storage modulus, loss modulus, glass transition temperature (T/sub g/), and moisture uptake of these underfill materials. Also, the key elements and steps of the solder-bumped flip-chips on low-cost substrates with these underfill materials such as the chip, printed circuit board (PCB), flip chip assembly, and underfill application are presented. Furthermore, the key elements and steps of the rework of the solder-bumped flip-chip assemblies with these underfill materials such as chip removal, chip reballing, substrate cleaning, and new chip placement are discussed. Finally, shear test results of the assemblies with one-time rework and no-rework are presented.     

Correlation between microstructure and drastically reduced lattice thermal conductivity in bismuth telluride/bismuth nanocomposites for high thermoelectric figure of merit

The concept of nanocomposite/nanostructuring in thermoelectric materials has been proven to be an effective paradigm for optimizing the high thermoelectric performance primarily by reducing the thermal conductivity. In this work, we have studied the microstructure details of nanocomposites derived by incorporating a semi-metallic Bi nanoparticle phase in Bi₂Te₃ matrix and its correlation mainly with the reduction in the lattice thermal conductivity. Incorporating Bi inclusion in Bi₂Te₃ bulk thermoelectric material results in a substantial increase in the power factor and simultaneous reduction in the thermal conductivity. The main focus of this work is the correlation of the microstructure of the composite with the reduction in thermal conductivity. Thermal conductivity of the matrix and nanocomposites was derived from the thermal diffusivity measurements performed from room temperature to 150 °C. Interestingly, significant reduction in total thermal conductivity of the nanocomposite was achieved as compared to that of the matrix. A detailed analysis of high-resolution transmission electron microscope images reveals that this reduction in the thermal conductivity can be ascribed to the enhanced phonon scattering by distinct microstructure features such as interfaces, grain boundaries, edge dislocations with dipoles, and strain field domains.     

Current reliability issues and future technologies for systems on silicon – processes, circuits, chip architecture, and design

The progress of silicon technology is opening the era of “systems on silicon” in which a large-scale memory, a CPU, and other logic macros will be integrated on a single chip. These kinds of chips, called system LSIs, have an especially promising future in mobile and multimedia applications but face inherent technical problems related to the reliability of ultrathin oxide film, conflict in the processing of different components, increased gate and subthreshold leakage currents, memory bottlenecks, and design complexity. This paper reviews the system LSIs and then introduces related technologies in processing, circuits, chip architecture, and design. It also discusses the influence of the system LSIs on business strategies.     

Deterministic annealing for clustering, compression,classification, regression, and related optimization problems

The deterministic annealing approach to clustering and its extensions has demonstrated substantial performance improvement over standard supervised and unsupervised learning methods in a variety of important applications including compression, estimation, pattern recognition and classification, and statistical regression. The application-specific cost is minimized subject to a constraint on the randomness of the solution, which is gradually lowered. We emphasize the intuition gained from analogy to statistical physics. Alternatively the method is derived within rate-distortion theory, where the annealing process is equivalent to computation of Shannon's rate-distortion function, and the annealing temperature is inversely proportional to the slope of the curve. The basic algorithm is extended by incorporating structural constraints to allow optimization of numerous popular structures including vector quantizers, decision trees, multilayer perceptrons, radial basis functions, and mixtures of experts     

The interdependence of geometrical, thermal, and electrical limitations for VLSI logic

With the trend towards further minimization, VLSI chips containing random logic will approach various fundamental limits. The interdependency of geometrical, thermal, and electrical effects is discussed, showing that a 1 cm/SUP 2/ chip is about equally limited by these three effects.     

New technology,communities, and networking: problems and prospects for orchestrating change

This paper discusses the concept of community networking using new technologies. It specifically focuses on relatively large-scale town networks, where the network has outside sponsorship, and provides some examples of these networks. After examining the motivation for community networks, we attempt to see to what extent local concerns are being met in these social experiments. Unfortunately, there is a serious shortage of evaluation studies on many of these networks. In the final third of the paper, we discuss in more detail the eircom Ennis Information Age Town (eEIAT) project in Ireland, and provide some information on an on-going project, in which we are involved, concerning the design of community networking centres.     

Rasterization theory,architectures, and implementations for a class of two-dimensional problems

This paper first presents a theory for rasterizing the class of two-dimensional problems which include signal/image processing, computer vision, and linear algebra. The rasterization theory is steered by an isomorphism relationship between the two-dimensional shuffle exchange network (2DSE) and the two-dimensional butterfly network (2DBN). Since in real-time applications, data are often acquired in a raster scan format, it is important to develop architectures to support the raster data structure. Algorithms are developed first by using 2DSE network, then transformed into 2DBN format. Rasterization architectures can be derived for the algorithms described by 2DBN format. In the PEACE project, we have been able to show that a single, fixed communication topology, namely 2DSE, provides solution times on a 2DSE parallel computing system that for many problems approach known theoretical lower bounds. Secondly, this paper presents the generic architectures and VLSI implementation examples for the rasterization structures.     

Bus encoder design for reduced crosstalk,power and area in coupled VLSI interconnects

This research work presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method is used to reduce inter-wire coupling, which is actually responsible for crosstalk, delay and power dissipation in coupled interconnects. The proposed method focuses on simplified and improved encoder circuit for 4, 8 and 16 coupled lines. In past, the researchers developed encoders that usually focused on minimizing power dissipation and/or crosstalk, thereby paying heavy penalty in terms of chip area. However, the proposed encoder and decoder while significantly reducing crosstalk demonstrates an overall reduction of power dissipation by 68.76% through drastically limiting switching activity. Furthermore, while reducing the complexity, chip area and transistor count of the circuit is reduced by more than 57%.     

QoS routing for wireless ad hoc networks: problems, algorithms, and protocols

QoS routing plays an important role for providing QoS in wireless ad hoc networks. The goals of QoS routing are in general twofold: selecting routes with satisfied QoS requirement(s), and achieving global efficiency in resource utilization. In this article we first discuss some key design considerations in providing QoS routing support, and present a review of previous work addressing the issue of route selection subject to QoS constraint(s). We then devise an on-demand delay-constrained unicast routing protocol. Various strategies are employed in the protocol to reduce the communication overhead in acquiring cost-effective delay-constrained routes. Simulation results are used to verify our expectation of the high performance of the devised protocol. Finally, we discuss some possible future directions for providing efficient QoS routing support in wireless ad hoc networks.     

Design,analysis and experimental investigations of a high precision flexure-based microgripper for micro/nano manipulation

In this paper, a flexure-based piezoelectric actuated microgripper is presented for high precision micro/nano manipulation tasks. A new design of microgripper based on a three-stage displacement amplification mechanism is utilized to magnify the piezoelectric actuator displacement. A bridge-type mechanism with a two-sided output port is serially connected with two consecutive lever mechanisms. The output motion on both sides is linearized by parallelogram mechanisms. The single-notch and double-notch circular flexural hinges were used in lever, bridge-type and parallelogram configuration. The displacement amplification and transmission mechanisms are arranged symmetrically to obtain stability of shape and compact layout of the entire microgripper. Analytical modeling was performed to establish an input and output displacement relationship. Finite Element Analysis (FEA) method was utilized to evaluate the performance of the microgripper. The design parameters of the microgripper were optimized through FEA method. The simulation results of the FEA method were validated through experimentation on the established design. The experimental results show that the total displacement amplification ratio of the microgripper is 12.76. The microgripper jaws have a high precision positioning accuracy. The microgripper also achieves a high-level working mode frequency of 1044 Hz, which is capable of accommodating rapid transient responses.