A new semi-flat architecture for high speed and reduced area CORDIC chip

In this contribution we present a new CORDIC architecture called ‘semi-flat’ which reduces considerably the latency time and the amount of hardware. In our semi-flat architecture the first rotations are executed with an unfolded scheme but the remaining iterations are flattened using a fast redundant addition tree. Detailed comparisons with other major contributions show that our semi-flat redundant CORDIC is 30% faster and occupy 39% less silicon area.     

芯片贴装用银浆料的热物理与力学性能

针对集成电路半导体芯片贴装,替代金-硅共熔焊或导电胶类粘结剂,研制了一种由银粉、玻璃粉和有机载体组成的低温烧结型银基浆料,其烧结温度峰值为430℃。研究了浆料的成分配比、工艺及其芯片贴装烧结工艺对浆料烧结体的微观组织、αL、λ、芯片组装的剪切力和热循环对芯片剪切力的影响规律。结果表明,当ζ(银粉:玻璃粉)=7:3,ζ(固体混合粉末:有机载体)=8:2时,芯片贴装后的综合性能最佳,冷热循环500次后其剪切力仅下降15%。     

Temperature measurements and thermal modeling of high power IGBT multichip modules for reliability investigations in traction applications

To study the failure mechanisms induced on high power IGBT multichip modules by thermal cycling stress in traction environment, a good knowledge of the temperature distribution and variations on the chips and in the interfaces between the different layers of the packaging is necessary. This paper presents a methodology for contact temperature measurements on chips surface in power cycling conditions and a fast 3D thermal simulation tool for multilayered hybrid or monolithic circuits. The results of static and dynamic thermal simulation of a 1200A–3300V IGBT module are given and compared with the contact temperature measurements results. The investigation has been done within the RAPSDRA (Reliability of Advanced High Power Semiconductor Device for Traction Applications) European project.     

DS-CDMA chip waveform design for minimal interference underbandwidth, phase, and envelope constraints

This paper investigates the effect of chip waveform shaping on the error performance, bandwidth confinement, phase continuity, and envelope uniformity in direct-sequence code-division multiple-access communication systems employing offset quadrature modulation formats. An optimal design methodology is developed for the problem of minimizing the multiple-access interference power under various desirable signal constraints, including limited 99% and 99.9% power bandwidth occupancies, continuous signal phase, and near-constant envelope. The methodology is based on the use of prolate spheroidal wave functions to obtain a reduced-dimension discrete constrained optimization problem formulation. Numerous design examples are discussed to compare the performance achieved by the optimally-designed chip waveforms with other conventional schemes, such as offset quadrature phase-shift keying, minimum-shift keying (MSK), sinusoidal frequency-shift keying (SFSK), and time-domain raised-cosine pulses. In general, it is found that while the optimized chip pulses achieved substantial gains when no envelope constraints were imposed, these gains vanish when a low envelope fluctuation constraint was introduced. In particular, it is also shown that MSK is quasi-optimal with regard to the 99% bandwidth measure, while the raised-cosine pulse is equally good with both the 99% and 99.9% measures, but at the expense of some envelope variation. On the other hand, SFSK is quasi-optimal with regard to the 99.9% bandwidth occupancy, among the class of constant-to-low envelope variation pulses     

TESTCHIP: a chip for weighted random pattern generation,evaluation, and test control

In self-testable circuits, additional hardware is incorporated for generating test patterns and evaluating test responses. A built-off test strategy is presented which moves the additional hardware to a programmable extra chip. This is a low-cost test strategy in three ways: (1) the use of random patterns eliminates the expensive test-pattern computation; (2) a microcomputer and an ASIC (application-specific IC) replace the expensive automatic test equipment; and (3) the design for testability overhead is minimized. The presented ASIC generates random patterns, applies them to a circuit under test, and evaluates the test responses by signature analysis. It contains a hardware structure that can produce weighted random patterns corresponding to multiple programmable distributions. These patterns give a high fault coverage and allow short test lengths. A wide range of circuits can be tested as the only requirement is a scan path and no other test structures have to be built in     

No-flow underfill process modeling and analysis for low cost, high throughput flip chip assembly

A new defect in which a chip "floats" over the board surface after chip placement is appearing in the low-cost, high-throughput flip chip on board (FCOB) assembly that is based on no-flow underfill. This defect has the potential to significantly lower process yield when process variables are not properly controlled. In fact, it was found that much of the yield loss observed post reflow is attributable to "chip floating." A process model has been developed that will allow an understanding of the underlying physics of the floating phenomena and identification of process variables so that this process defect can be eliminated. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was specially designed so that chip floating over the board can be easily detected. To validate the model, the effects of the critical process variables on chip floating were investigated by a series of experiments, and the results were compared to the theoretical model's predictions.     

Characteristics and reliability of fast-flow, snap-cure, and reworkable underfills for solder bumped flip chip on low-cost substrates

In this study, the fast-flow, fast-cure, and reworkable underfill materials from two different vendors are considered. Emphasis is placed on the determination of the curing conditions such as temperature and time, and the material properties such as the thermal coefficient of expansion (TCE), storage modulus, loss modulus, glass transition temperature (T/sub g/), and moisture uptake of these underfill materials. Also, the key elements and steps of the solder-bumped flip-chips on low-cost substrates with these underfill materials such as the chip, printed circuit board (PCB), flip chip assembly, and underfill application are presented. Furthermore, the key elements and steps of the rework of the solder-bumped flip-chip assemblies with these underfill materials such as chip removal, chip reballing, substrate cleaning, and new chip placement are discussed. Finally, shear test results of the assemblies with one-time rework and no-rework are presented.     

Current reliability issues and future technologies for systems on silicon – processes, circuits, chip architecture, and design

The progress of silicon technology is opening the era of “systems on silicon” in which a large-scale memory, a CPU, and other logic macros will be integrated on a single chip. These kinds of chips, called system LSIs, have an especially promising future in mobile and multimedia applications but face inherent technical problems related to the reliability of ultrathin oxide film, conflict in the processing of different components, increased gate and subthreshold leakage currents, memory bottlenecks, and design complexity. This paper reviews the system LSIs and then introduces related technologies in processing, circuits, chip architecture, and design. It also discusses the influence of the system LSIs on business strategies.     

The interdependence of geometrical, thermal, and electrical limitations for VLSI logic

With the trend towards further minimization, VLSI chips containing random logic will approach various fundamental limits. The interdependency of geometrical, thermal, and electrical effects is discussed, showing that a 1 cm/SUP 2/ chip is about equally limited by these three effects.     

Deterministic annealing for clustering, compression,classification, regression, and related optimization problems

The deterministic annealing approach to clustering and its extensions has demonstrated substantial performance improvement over standard supervised and unsupervised learning methods in a variety of important applications including compression, estimation, pattern recognition and classification, and statistical regression. The application-specific cost is minimized subject to a constraint on the randomness of the solution, which is gradually lowered. We emphasize the intuition gained from analogy to statistical physics. Alternatively the method is derived within rate-distortion theory, where the annealing process is equivalent to computation of Shannon's rate-distortion function, and the annealing temperature is inversely proportional to the slope of the curve. The basic algorithm is extended by incorporating structural constraints to allow optimization of numerous popular structures including vector quantizers, decision trees, multilayer perceptrons, radial basis functions, and mixtures of experts     

Bus encoder design for reduced crosstalk,power and area in coupled VLSI interconnects

This research work presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method is used to reduce inter-wire coupling, which is actually responsible for crosstalk, delay and power dissipation in coupled interconnects. The proposed method focuses on simplified and improved encoder circuit for 4, 8 and 16 coupled lines. In past, the researchers developed encoders that usually focused on minimizing power dissipation and/or crosstalk, thereby paying heavy penalty in terms of chip area. However, the proposed encoder and decoder while significantly reducing crosstalk demonstrates an overall reduction of power dissipation by 68.76% through drastically limiting switching activity. Furthermore, while reducing the complexity, chip area and transistor count of the circuit is reduced by more than 57%.     

QoS routing for wireless ad hoc networks: problems, algorithms, and protocols

QoS routing plays an important role for providing QoS in wireless ad hoc networks. The goals of QoS routing are in general twofold: selecting routes with satisfied QoS requirement(s), and achieving global efficiency in resource utilization. In this article we first discuss some key design considerations in providing QoS routing support, and present a review of previous work addressing the issue of route selection subject to QoS constraint(s). We then devise an on-demand delay-constrained unicast routing protocol. Various strategies are employed in the protocol to reduce the communication overhead in acquiring cost-effective delay-constrained routes. Simulation results are used to verify our expectation of the high performance of the devised protocol. Finally, we discuss some possible future directions for providing efficient QoS routing support in wireless ad hoc networks.     

Novel low-cost ultra-wideband, ultra-short-pulse transmitter withMESFET impulse-shaping circuitry for reduced distortion and improvedpulse repetition rate

A new ultra-wideband, ultra-short-pulse transmitter has been developed using microstrip lines, step-recovery and Schottky diodes, MESFET, and monolithic microwave integrated circuit (MMIC) amplifier. This transmitter employs a novel MESFET impulse-shaping circuit to achieve several unique advantages, including less distortion, easy broadband matching, and increased pulse repetition rate. The transmitter produces 300-ps monocycle pulses with about 2 V peak-to-peak and a pulse repetition rate of 10 MHz. The measured pulses have good symmetry and low ringing level     

THERMAN: a thermal simulation tool for IC chips, microstructures and PW boards

This article presents THERMAN: the renewed version of the μS-THERMANAL simulation program. The program was rewritten last year, in order to include algorithmic novelties such as time-constant analysis. The new code is fully transportable providing the same user interface on PCs and on Unix-based workstations. The graphical interface allows a fast problem definition and easy, many-sided evaluation of the results.     

General entropy criteria for inverse problems, with applications todata compression, pattern classification, and cluster analysis

Minimum distance approaches are considered for the reconstruction of a real function from finitely many linear functional values. An optimal class of distances satisfying an orthogonality condition analogous to that enjoyed by linear projections in Hilbert space is derived. These optimal distances are related to measures of distances between probability distributions recently introduced by C.R. Rao and T.K. Nayak (1985) and possess the geometric properties of cross entropy useful in speech and image compression, pattern classification, and cluster analysis. Several examples from spectrum estimation and image processing are discussed     

Fast convolution based thermal model for 3D-ICs: Methodology,accuracy analysis and package impact

Thermal analysis is essential in 3D-IC technology due to the reduced footprint and higher power densities compared to conventional 2D packaging. Computationally fast thermal models (FTMs) are being developed for fast evaluation of the temperature distribution in 3D packages. The steady state FTM discussed in this paper is based on Green׳s function theory and exploits convolution and the fast Fourier transform to compute the temperature profiles starting from matrices storing the power dissipation densities (power maps) and the temperature responses to hot spots. However, this methodology is not directly applicable for finite dimensional structures. The method of images is exploited to include the effect of insulating lateral boundary conditions. The number of images needed to ensure accurate results depends on the specific structure of the stack. A fast method to compute it is proposed together with a short analysis of its dependence on some system parameters. A two dies stack case study is thermally analyzed showing good agreement with the finite element method (FEM) results (errors less than 0.5%). The computational time is also discussed indicating a $O(N\log N)$ behavior, where N is the number of elements in the extended power maps, which include images, as well as a 70 times speed up with respect to FEM. Finally, since in the FTM the package is implicitly included in the boundary conditions, the thermal impact of its real configuration is investigated.     

Optimal replacement policy (N, n) for a parallel system with common cause failure and geometric repair time

The purpose of this article is to present an improved replacement model for a parallel system of N identical units, by bringing in common cause failure (CCF), maintenance cost and repair cost per unit time additionally, and to develop a procedure to obtain the optimal redundant units N^* and optimal number of repairs n^* with the conditions that the system is allowed to undergo at most a prefixed number of repairs before to be replaced and the successive reapir times after failures constitute a non-decreasing Geometric process. Several conditions for the existence of the optimal N^* and n^* is stated and the results are illustrated by a numerical example.     

A 915-MHz antenna for microwave thermal ablation treatment: physical design, computer modeling and experimental measurement

A 915-MHz antenna design that produces specific absorption rate distributions with preferential power deposition in tissues surrounding and including the distal end of the catheter antenna is described. The design features minimal reflected microwave current from the antenna flowing up the transmission line. This cap-choke antenna consists of an annular cap and a coaxial choke which matches the antenna to the coaxial transmission line. The design minimizes heating of the coaxial cable and its performance is not affected by the depth of insertion of the antenna into tissue. The paper provides a comparison of results obtained from computer modeling and experimental measurements made in tissue equivalent phantom materials. There is excellent agreement between numerical modeling and experimental measurement. The cap-choke, matched-dipole type antenna is suitable for intracavitary microwave thermal ablation therapy.