CMOS数字锁相环中的自校准技术

提出了一种数字锁相环(DPLL).该电路采用自校准技术,具有快速锁定、低抖动、锁定频率范围宽等优点.设计的锁相环在1.8 V外加电源电压时,工作在60～600 MHz宽的频率范围内.电路采用5层金属布线的0.18 μm CMOS工艺制作.测试结果显示,电路的峰-峰抖动小于输出信号周期(Tout)的0.5%,锁相环锁定时间小于参考时钟预分频后信号周期(Tpre)的150倍.     

一种具有自校准功能的CMOS分数数字锁相环

提出了一种数字锁相环(DPLL),它的相频检测器采用全新的设计方法和自校准技术,具有工作频率范围宽,抖动低,快速锁定的优点.锁相环在1.8V外加电源电压时,工作在60～600MHz的频率范围内.采用分数分频技术,加速锁定过程并具有较小的输出频率间隔,利用∑-Δ调制改善相位噪声性能.设计在SMIC 0.18μm,1.8V,1P6M标准CMOS工艺上实现,峰-峰相位抖动小于输出信号周期的0.8%,锁相环的锁定时间小于参考频率预分频后信号周期的150倍.     

一种具有自校准功能的CMOS分数数字锁相环

提出了一种数字锁相环(DPLL),它的相频检测器采用全新的设计方法和自校准技术,具有工作频率范围宽,抖动低,快速锁定的优点.锁相环在1.8V外加电源电压时,工作在60～600MHz的频率范围内.采用分数分频技术,加速锁定过程并具有较小的输出频率间隔,利用∑-Δ调制改善相位噪声性能.设计在SMIC 0.18μm,1.8V,1P6M标准CMOS工艺上实现,峰-峰相位抖动小于输出信号周期的0.8%,锁相环的锁定时间小于参考频率预分频后信号周期的150倍.     

基于锁定时间分析的锁相环频率合成器

提出了一种新的针对采用二阶无源滤波器的锁相环频率合成器锁定时间的估算公式,并通过仿真软件及实测结果对该公式进行了验证。基于该估算公式,设计了一种具有快速锁定功能的锁相环频率合成器。实验结果表明该锁相环频率合成器锁定时间小于7μs,具有快速锁定的功能。同时该锁相环还具有良好的相位噪声性能,对于32GHz输出信号相位噪声为-72dBc/Hz@1kHz以及-90dBc/Hz@1MHz。     

万兆以太网物理层全集成单片锁相环电路

给出了一个采用 0 .2μm Ga As PHEMT工艺实现的单片集成高速锁相环电路。芯片采用差分电感电容谐振式负跨导压控振荡器 ,总面积为 0 .9mm× 0 .7mm。采用 3.3V单电源供电 ,测得芯片总功耗为 2 83m W,输出功率约 - 1 1 d Bm,中心频率 7.2 GHz,锁定范围为± 30 0MHz。环路锁定在 7.2 GHz时 ,输出信号的峰 -峰抖动约 5 .6ps,在 5 0 k Hz频偏处的单边带相位噪声为 - 94d Bc/Hz。本锁相环电路经适当修改可应用于万兆以太网物理层 IEEE80 2 .3ae1 0 GBASE- R或 1 0 GBASE- W时钟恢复电路。     

精密频率与相位调整方法

精密频率与相位调整技术是守时系统的关键技术。利用直接数字频率合成(DDS)引入精密频率与相位调整量,通过锁相环将DDS输出锁定于本地恒温晶振OCXO,在锁相环中通过分频和两级频差倍增提升频率和相位调整分辨率,环路锁定后的OCXO输出即频率和相位精密微调后的信号。设计了基于相位比对的频率和相位调整分辨率测试系统,实验结果表明,精密频率与相位调整系统的频率调整分辨率达到了4×10-17,相位调整分辨率达到了6 fs。     

GPS接收机中1.57 GHz CMOS锁相环的设计

设计了一种用于GPS接收机中采用CMOS工艺实现的1.57GHz锁相环.其中,预分频器采用高速钟控锁存器(LATCH)的结构,工作频率超过2GHz.VCO中采用LC谐振回路,具有4段连续的调节范围,输出频率范围可以达到中心频率的20%.电荷泵采用一种改进型宽摆幅自校准电路,可以进一步降低环路噪声.锁相环采用0.25μmRFCOMS工艺实现.测量表明VCO输出在偏移中心频率1MHz处的相位噪声为-110dBc/Hz,锁相环输出在偏移中心频率10kHz处的相位噪声小于-90dBc/Hz.供电电压为2.5V时,功耗小于15mW.     

基于PI控制的全数字锁相环设计

针对以往全数字锁相环研究中所存在电路结构复杂、设计难度较大和系统性能欠佳等问题,提出了一种实现全数字锁相环的新方法。该锁相环以数字比例积分控制的设计结构取代了传统的一些数字环路滤波控制方法。应用EDA技术完成系统设计,并进行计算机仿真。仿真结果表明:在一定的频率范围内,该锁相环锁定时间最长小于15个输入信号周期,相位抖动小于输出信号周期的5%,且具有电路结构简单、环路性能好和易于集成的特点。     

一种-62.3 dBc参考杂散6 GHz低功耗锁相环

采用高匹配电荷泵电路和高精度自动频率校准(AFC)电路,设计了一种低功耗低参考杂散电荷泵锁相环。锁相环包括D触发鉴频鉴相器、5 bit数字可编程调频LC压控振荡器(VCO)、16～400可编程分频器和AFC模块。采用高匹配电荷泵,通过增大电流镜输出阻抗的方法,减少电荷泵充放电失配。同时,AFC电路采用频段预选快速搜索方法,实现了低压控增益LC VCO精确频带锁定,扩展了振荡频率范围,且保持了较低的锁相环输出参考杂散。锁相环基于40 nm CMOS工艺设计,电源电压为1.1 V。仿真结果表明,电压匹配范围为0.19～0.88 V,振荡频率范围为5.9～6.4 GHz,功率小于6.5 mW@6 GHz,最大电流失配小于0.2%@75μA;当输出信号频率为6 GHz时,输出相位噪声为-113.3 dBc/Hz@1 MHz,参考杂散为-62.3 dBc。     

一种应用于HDMI接收端的宽频带锁相环设计

基于110 nm CMOS工艺设计了一种应用于HDMI接收端电路的宽频带低抖动锁相环。采用一种改进型双环结构电荷泵,在25～250 MHz的宽输入频率范围内实现了快速锁定。通过高相噪性能的伪差分环形振荡器产生了调谐范围为125 MHz～1.25 GHz的时钟信号。仿真实验结果表明,该锁相环的锁定时间小于1.2μs,在振荡器工作频率为0.8 GHz时,其相位噪声为-100.0 dBc/Hz@1 MHz,输出时钟峰峰值抖动为4.49 ps。     

Shannon定理在数字锁相环中的应用

传统的数字锁相环（ＤＰＬＬ）多采用吞脉冲的方法来实现ＤＣＯ,此方法要求工作频率远高于ＤＰＬＬ的输出频率。采用Ｓｈａｎｎｏｎ定理并结合延时抽头技术设计的ＤＰＬＬ,可使ＤＰＬＬ的输出频率接近工作频率。如采用２０ＭＨＺ的主时钟可以产生１６．３８４ＭＨＺ、１２．３５２ＭＨＺ甚至１９．４４ＭＨＺ的频率信号,且能获得较高的频率精度度。同时,本例采用了自适应误差补偿技术,可补偿工艺偏差,同时也可实时补偿由于温度     

LSI's for digital signal processing

This paper describes high-performance CMOS LSI's for digital signal-processing (DSP) technology, such as digital filter, fast Fourier transform (FFT), discrete Fourier transform (DFT), and digital phase-locked loop (DPLL). First, DSP functions for communication use, functional blocks to compose DSP functions, and the types of arithmetic for LSI are discussed. It is explained that multiplier (MPL), variable-length shift register (VSR), and linear arithmetic processor (LAP) have been chosen as the most useful DSP LSI's. Device design for high-speed and low-power CMOS is described and its feasibility is shown as characteristics of propagation delay time at 430 ps and power delay product at 0.073 pJ. The 3-µm effective channel-length CMOS technology has been selected for the DSP LSI because of the high speed, 5 ns, in the case of two input NAND gates and high yield technology. The multiplier architecture is pipeline and uses the Two's-complement representative, the variable-length shift register uses the binary-select method, and the linear arithmetic processor uses the method of changing the outside connections for realization of DSP functions. Maximum operating frequency of these LSI's is more than 23 MHz at the 5-V source voltage. Power dissipation of a VSR, which has been lossy, is less than 250 mW in the 8-MHz operation. They have wider application to communication systems. High-speed CMOS technology is applied to the digital system equipment up to the second level of the PCM hierarchy.     

LSIs for digital signal processing

The authors describe high-performance CMOS LSIs for digital signal-processing (DSP) technology, such as digital filter, fast Fourier transform (FFT), discrete Fourier transform (DFT), and digital phase-locked loop (DPLL), for communication use. Device design for high-speed and low-power CMOS is described and its feasibility is shown as characteristics of propagation delay time and power delay product.     

Performance Analysis of Digital Tanlock Loop

In this paper, a nonuniform-sampling digital phaselocked loop (DPLL) called the digital tanlock loop (DTL), which uses a new type of phase error detector with linear phase characteristic, is studied. The main feature of the DTL is that the phase error detector, using thetan^{-1}(.)function with in-phase and quadrature samples of the incoming signal, has a linear characteristic with a period of 2π. Accordingly, the DTL can be characterized by a linear difference equation, thereby making it possible to analyze the loop easily, without approximation of nonlinearity as is usually done in analysis of a conventional DPLL with sinusoidal phase characteristic. The performances of the first- and second-order DTL's in the absence and presence of noise have been investigated by analysis and computer simulation. It is shown that the linear phase characteristic results in many attractive features in comparison to the conventional DPLL with the sinusoidal phase characteristic. These include insensitivity of the locking conditions to variation of input signal power, more noise immunity, wider lock range and less steady-state phase error of the first-order loop for an input with frequency offset, and much less sensitivity to initial phase errors in convergence of the second-order loop.     

A high lock-in speed digital phase-locked loop

A digital phase-locked loop (DPLL) consisting of a modified 9-gate phase detector, a frequency multiplier, and a loop filter is described. All the components are implemented in digital hardware. The Z-transform is employed to deduce the system function, and some simple properties of the DPLL are inferred by examining the mathematical model. The advantages of the proposed DPLL are: high lock-in speed, no steady-state frequency tracking error even for period ramp input signals; and ease of integration into a single chip. The use of the DPLL to realize the pitch synchronous analysis of voiced speech is reported     

1-V power supply high-speed digital circuit technology withmultithreshold-voltage CMOS

1-V power supply high-speed low-power digital circuit technology with 0.5-μm multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-μW/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-μm CMOS process     

基于VHDL的一种改进型数字锁相环的设计与实现

研究了一种用估计周期值来调整计数器和控制器的改进型数字锁相环的实现方案。介绍了改进型数字锁相环的原理,详细分析各组成部分的性能,最后给出基于VHDL语言的实现过程。仿真结果表明,设计的锁相环具有宽频带、大相差、捕获时间短、性能稳定的特点。     

A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications

This paper presents a low-power wideband signaling (WBS) digital transceiver for data transmission through a human body for body area network applications. The low-power and highspeed human body communication (HBC) utilizes a digital transceiver chip based on WBS and adopts a direct-coupled interface (DCI) which uses an electrode of 50-Omega impedance. The channel investigation with the DCI identities an optimum channel bandwidth of 10 kHz to 100 MHz. The WBS digital transceiver exploits a direct digital transmitter and an all-digital clock and data recovery (CDR) circuit. To further reduce power consumption, the proposed CDR circuit incorporates a low-voltage digitally-controlled oscillator and a quadratic sampling technique. The WBS digital transceiver chip with a 0.25-mum standard CMOS technology has 2-Mb/s data rate at a bit error rate of 1.1 times 10^-7, dissipating only 0.2 mW from a 1-V supply generated by a 1.5-V battery.     

A 1/2-in, 1.3 M-pixel progressive-scan CCD image sensor employing0.25-μm gap single-layer poly-Si electrodes

A 1/2-in, 1.3 M-pixel progressive-scan interline-transfer charge coupled-device (IT-CCD) image sensor has been developed for low-power and high-sensitivity digital cameras. The image sensor uses 0.25-μm gap single-layer poly-Si for CCD transfer electrodes in order to reduce the power consumption and number of fabrication process steps. The image sensor achieved a low driving voltage (2.1 V) on a horizontal CCD (H-CCD) at a frequency of 24.5 MHz. An original pixel layout and a self-aligned photodiode structure make it possible to achieve a progressive scan pixel with well-controlled photodiode readout characteristics. An output three-stage source follower amplifier with new multioxide transistors, whose gate insulator thickness is thinner than that of a CCD register, is able to attain 17% higher gain than that of the conventional amplifier. The sensor provides low-power (100 mW) and high output sensitivity. The total number of steps for fabricating the sensor was reduced to 70% of that for conventional three-layer poly-Si electrodes