Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage Device Structure

A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are presented. The structure is characterized by a compound buried layer (CBL) made of two oxide layers and a polysilicon layer between them. At the high-voltage blocking state, holes collected on the polysilicon bottom interface shield the SOI layer and the upper buried oxide (UBO) layer from the back-gate bias $V_{rm bg}$, resulting in a constant breakdown voltage (BV) and the same electric field and potential distributions in the SOI layer, UBO, and polysilicon under different the back-gate biases for a CBL SOI REduced SURface Field (RESURF) Lateral Double-diffused MOS (LDMOS). $V_{rm bg}$ only impacts the field strength and voltage drop in the lower buried oxide (LBO) layer. Moreover, based on the continuity of electric displacement, the holes enhance the field in the LBO from 80 $hbox{V}/muhbox{m}$ of the conventional SOI to 457 $hbox{V}/muhbox{m}$ at $V_{rm bg} = hbox{0 V}$, leading to a high BV. A 747-V CBL SOI LDMOS is fabricated, and its eliminating back-gate bias effect is verified by measurement. In addition, the CBL SOI structure can alleviate the self-heating effects due to a window in the UBO.      

Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a $hbox{Si} hbox{p}^{+}{-}hbox{i}{-} hbox{n}^{+}$ tunneling junction, the TFET with a gate length of $sim$200 nm exhibits good subthreshold swing of $sim$ 70 mV/dec, superior drain-induced-barrier-lowering of $sim$ 17 mV/V, and excellent $I_{rm on} {-} I_{rm off}$ ratio of $sim!!hbox{10}^{7}$ with a low $I_{rm off} (sim!!hbox{7} hbox{pA}/muhbox{m})$. The obtained 53 $muhbox{A}/muhbox{m} I_{rm on}$ can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.      

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

Novel Low-$k$ Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI

A high-voltage lateral double diffused metal–oxide–semiconductor transistor on partial silicon on insulator (PSOI) with a buried low-$k$ dielectric (LK PSOI) is proposed. The low-$k$ value enhances the electric field strength in the dielectric $(E_{I})$. The Si window not only makes the substrate share the breakdown voltage (BV) and modulates the field distribution in the SOI layer but also alleviates the self-heating effect. Compared with those of the conventional PSOI, the $E_{I}$ and BV of LK PSOI with $k_{I} = hbox{2}$ are enhanced by 74% and 19%, respectively.      

High Microwave-Noise Performance of AlGaN/GaN MISHEMTs on Silicon With Gate Insulator Grown by ALD

High microwave-noise performance is realized in AlGaN/GaN metal–insulator semiconductor high-electron mobility transistors (MISHEMTs) on high-resistivity silicon substrate using atomic-layer-deposited (ALD) $hbox{Al}_{2}hbox{O}_{3}$ as gate insulator. The ALD $hbox{Al}_{2}hbox{O}_{3}/hbox{AlGaN/GaN}$ MISHEMT with a 0.25- $muhbox{m}$ gate length shows excellent microwave small signal and noise performance. A high current-gain cutoff frequency $f_{T}$ of 40 GHz and maximum oscillation frequency $f_{max}$ of 76 GHz were achieved. At 10 GHz, the device exhibits low minimum-noise figure $(hbox{NF}_{min})$ of 1.0 dB together with high associate gain $(G_{a})$ of 10.5 dB and low equivalent noise resistance $(R_{n})$ of 29.2 $Omega$. This is believed to be the first report of a 0.25-$muhbox{m}$ gate-length GaN MISHEMT on silicon with such microwave-noise performance. These results indicate that the AlGaN/GaN MISHEMT with ALD $hbox{Al}_{2}hbox{O}_{3}$ gate insulator on high-resistivity Si substrate is suitable for microwave low-noise applications.      

CMOS Avalanche Photodiode Embedded in a Phase-Shift Laser Rangefinder

This paper presents the design and the characterization of a CMOS avalanche photodiode (APD) working as an optoelectronic mixer. The $hbox{P}^{+}hbox{N}$ photodiode has been implemented in a commercial 0.35-$muhbox{m}$ CMOS technology after optimization with SILVACO. The surface of the active region is $ hbox{3.78} cdot hbox{10}^{-3} hbox{cm}^{2}$. An efficient guard-ring structure has been created using the lateral diffusion of two n-well regions separated by a gap of 1.2 $mu hbox{m}$. When biased at $-$2 V, the best responsitivity $S_{lambda ,{rm APD}} = hbox{0.11} hbox{A/W}$ is obtained at $lambda = hbox{500} hbox{nm}$. This value can easily be improved by using an antireflection coating. At $lambda = hbox{472} hbox{nm}$, the internal gain is about 75 at $-$6 V and 157 at $-$7 V. When biased at $-$6 V, the APD achieves a dark current of 128 $muhbox{A} cdot hbox{mm}^{-2}$ and an excess noise factor $F = hbox{20}$ . Then, the APD is successfully used as an optoelectronic mixer to improve the signal-to-noise ratio of a low-voltage embedded phase-shift laser rangefinder.      

High-Density and Low-Leakage-Current MIM Capacitor Using Stacked $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Insulators

We have fabricated high-$kappa hbox{Ni}/hbox{TiO}_{2}/hbox{ZrO}_{2}/ hbox{TiN}$ metal–insulator–metal (MIM) capacitors. A low leakage current of $hbox{8} times hbox{10}^{-8} hbox{A/cm}^{2}$ at 125 $^{circ}hbox{C}$ was obtained with a high 38- $hbox{fF}/muhbox{m}^{2}$ capacitance density and better than the $hbox{ZrO}_{2}$ MIM capacitors. The excellent device performance is due to the lower electric field in 9.5-nm-thick $hbox{TiO}_{2}/ hbox{ZrO}_{2}$ devices to decrease the leakage current and to a higher $kappa$ value of 58 for $ hbox{TiO}_{2}$ as compared with that of $hbox{ZrO}_{2}$ to preserve the high capacitance density.      

Breakdown Enhancement of AlGaN/GaN HEMTs on 4-in Silicon by Improving the GaN Quality on Thick Buffer Layers

We have achieved a 9- $muhbox{m}$-thick AlGaN/GaN high-electron mobility transistor (HEMT) epilayer on silicon using thick buffer layers with reduced dislocation density $(D_{D})$. The crack-free 9- $muhbox{m}$-thick epilayer included 2- $muhbox{m}$ i-GaN and 7- $ muhbox{m}$ buffer. The HEMTs fabricated on these devices showed a maximum drain–current density of 625 mA/mm, transconductance of 190 mS/mm, and a high three-terminal OFF breakdown of 403 V for device dimensions of $L_{g}/W_{g}/L_{rm gd} = hbox{1.5/15/3} muhbox{m}$ . Without using a gate field plate, this is the highest $BV$ reported on an AlGaN/GaN HEMT on silicon for a short $L_{rm gd}$ of 3 $muhbox{m}$. A very high $BV$ of 1813 V across 10- $mu hbox{m}$ ohmic gap was achieved for i-GaN grown on thick buffers. As the thickness of buffer layers increased, the decreased $D_{D}$ of GaN and increased resistance between surface electrode and substrate yielded a high breakdown.      

Electrical Properties of Amorphous $hbox{Bi}_{5} hbox{Nb}_{3}hbox{O}_{15}$ Thin Film for RF MIM Capacitors

Amorphous $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}(hbox{B}_{5} hbox{N}_{3})$ film grown at 300 $^{circ}hbox{C}$ showed a high-$k$ value of 71 at 100 kHz, and similar $k$ value was observed at 0.5–5.0 GHz. The 80-nm-thick film exhibited a high capacitance density of 7.8 fF/$muhbox{m}^{2}$ and a low dissipation factor of 0.95% at 100 kHz with a low leakage-current density of 1.23 nA/ $hbox{cm}^{2}$ at 1 V. The quadratic and linear voltage coefficient of capacitances of the $hbox{B}_{5}hbox{N}_{3}$ film were 438 ppm/$hbox{V}^{2}$ and 456 ppm/V, respectively, with a low temperature coefficient of capacitance of 309 ppm/$^{circ}hbox{C}$ at 100 kHz. These results confirmed the potential of the amorphous $hbox{B}_{5}hbox{N}_{3}$ film as a good candidate material for a high-performance metal–insulator–metal capacitors.      

High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Newly proposed mobility-booster technologies are demonstrated for metal/high- $k$ gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter gate lengths in comparison with a conventional gate-first process. Dummy gate removal in the damascene gate process induces high channel stress, because of the elimination of reaction force from the dummy gate. PFETs with top-cut compressive stress liners and embedded SiGe source/drains are performed by using atomic layer deposition TiN/$ hbox{HfO}_{2}$ gate stacks with $T_{rm inv} = hbox{1.4} hbox{nm}$ on (100) substrates. On the other hand, nFETs with top-cut tensile stress liners are obtained by using $hbox{HfSi}_{x}/hbox{HfO}_{2}$ gate stacks with $T_{rm inv} = hbox{1.4} hbox{nm}$. High-performance n- and pFETs are achieved with $I_{rm on} = hbox{1300}$ and 1000 $muhbox{A}/muhbox{m} hbox{at} I_{rm off} = hbox{100} hbox{nA}/mu hbox{m}$, $V_{rm dd} = hbox{1.0} hbox{V}$, and a gate length of 40 nm, respectively.      

0.8-V Supply Voltage Deep-Submicrometer Inversion-Mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFET

We report the experimental demonstration of deep-submicrometer inversion-mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFETs with ALD high- $k$ $hbox{Al}_{2}hbox{O}_{3}$ as gate dielectric. In this letter, n-channel MOSFETs with 100–200-nm-long gates have been fabricated. At a supply voltage of 0.8 V, the fabricated devices with 200–130-nm-long gates exhibit drain currents of 232–440 $muhbox{A}/muhbox{m}$ and transconductances of 538–705 $muhbox{S}/muhbox{m}$. The 100-nm device has a drain current of 801 $muhbox{A}/muhbox{m}$ and a transconductance of 940 $muhbox{S}/muhbox{m}$. However, the device cannot be pinched off due to severe short-channel effect. Important scaling metrics, such as on/off current ratio, subthreshold swing, and drain-induced barrier lowering, are presented, and their relations to the short-channel effect are discussed.      

Photosensitive Inverter and Ring Oscillator With Pseudodepletion Mode Load for LCD Applications

Photosensitive inverters and ring oscillators (ROs) with pseudodepletion mode loads (PDMLs) were integrated in LCD panels using conventional mass production processes. The delay time $(t_{rm pd})$ of five-stage ROs with PDML reduced from 204.3 $mu hbox{s}$ under dark to 16.3 $muhbox{s}$ under backlight illumination of 20 000 lx. The oscillation frequency exhibited a power-law dependence $(f_{rm osc} infty hbox{IL}^{gamma})$ on the backlight illuminance with the extracted fitting parameter $gamma = hbox{0.447}$ at room temperature.      

High-Frequency ZnO Thin-Film Transistors on Si Substrates

Record microwave frequency performance was achieved with nanocrystalline ZnO thin-film transistors fabricated on Si substrates. Devices with 1.2-$muhbox{m}$ gate lengths and Au-based gate metals had current and power gain cutoff frequencies of $f_{T} = hbox{2.45} hbox{GHz}$ and $f_{max} = hbox{7.45} hbox{GHz}$ , respectively. Same devices had drain–current on/off ratios of $hbox{5} times hbox{10}^{10}$, exhibited no hysteresis effects and could be operated at a current density of 348 mA/mm. The microwave performances of devices with 1.2- and 2.1- $muhbox{m}$ gate lengths and 50- and 100-$muhbox{m}$ gate widths were compared.      

Punchthrough Enhanced Phototransistor Fabricated in Standard CMOS Process

A simple lateral structure phototransistor, combined with a normal phototransistor and a punchthrough transistor, has been successfully designed and fabricated in standard commercial CSMC 0.5- $muhbox{m}$ CMOS process. The proposed punchthrough enhancement mechanism provides a high optical gain of close to $hbox{10}^{7}$ for a low-level optical power of $hbox{7.0} times hbox{10}^{-15} hbox{W}$ at a wavelength of 650 nm. Compared with conventional punchthrough phototransistors, a lower dark current of around 1 $muhbox{A}$ is obtained at a 2.0-V operating voltage.      

High-Performance 0.1-$muhbox{m}$ Gate AlGaN/GaN HEMTs on Silicon With Low-Noise Figure at 20 GHz

The realization of high-performance 0.1-$muhbox{m}$ gate AlGaN/GaN high-electron mobility transistors (HEMTs) grown on high-resistivity silicon substrates is reported. Our devices feature cutoff frequencies as high as $f_{T} = hbox{75} hbox{GHz}$ and $f_{rm MAX} = hbox{125} hbox{GHz}$, the highest values reported so far for AlGaN/GaN HEMTs on silicon. The microwave noise performance is competitive with results achieved on other substrate types, such as sapphire and silicon carbide, with a noise figure $F = hbox{1.2}{-}hbox{1.3} hbox{dB}$ and an associated gain $G_{rm ass} = hbox{8.0}{-}hbox{9.5} hbox{dB}$ at 20 GHz. This performance demonstrates that GaN-on-silicon technology is a viable alternative for low-cost millimeter-wave applications.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

Comparative Study of the Low-Frequency-Noise Behaviors in a-IGZO Thin-Film Transistors With $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Gate Dielectrics

A comparative study is made of the low-frequency noise (LFN) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ gate dielectrics. The LFN is proportional to $hbox{1}/f^{gamma}$, with $gamma sim hbox{1}$ for both devices, but the normalized noise for the $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ device is two to three orders of magnitude lower than that for the $hbox{Al}_{2} hbox{O}_{3}$ device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices. The $hbox{SiN}_{x}$ interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the $hbox{Al}_{2}hbox{O}_{3}$ dielectric. Hooge's parameter is extracted to $sim !!hbox{6.0} times hbox{10}^{-3}$ in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices.      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

An Analytical Method to Extract the Physical Parameters of a Solar Cell From Four Points on the Illuminated $J{-}V$ Curve

For a variety of solar cells, it is shown that the single exponential $J{-}V$ model parameters, namely—ideality factor $eta$ , parasitic series resistance $R_{s}$, parasitic shunt resistance $R_{rm sh}$, dark current $J_{0}$, and photogenerated current $J_{rm ph}$ can be extracted simultaneously from just four simple measurements of the bias points corresponding to $V_{rm oc}$, $sim!hbox{0.6}V_{rm oc}$, $J_{rm sc}$, and $sim! hbox{0.6}J_{rm sc}$ on the illuminated $J{-}V$ curve, using closed-form expressions. The extraction method avoids the measurements of the peak power point and any $dJ/dV$ (i.e., slope). The method is based on the power law $J{-}V$ model proposed recently by us.      

Electrical Properties of $hbox{Ga}_{2}hbox{O}_{3}/ hbox{GaAs}$ Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs

Electrical properties of $hbox{Ga}_{2}hbox{O}_{3}/hbox{GaAs}$ interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm ($hbox{0.9} leq hbox{EOT} leq hbox{3.9} hbox{nm}$) have been characterized by capacitance–voltage measurements. Midgap interface state density $D_{rm it}$, effective workfunction $phi_{m}$, fixed charge $Q_{f}$, dielectric constant $kappa$, and low field leakage current density are $hbox{2} times hbox{10}^{11} hbox{cm}^{-2} cdot hbox{eV}^{-1}$, 4.93 eV, $-hbox{8.9} times hbox{10}^{11} hbox{cm}^{-2}$, 19.5, and $hbox{10}^{-9}{-} hbox{10}^{-8} hbox{A/cm}^{2}$, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.