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刍议数字电子电路的调试方法 总被引:1,自引:0,他引:1
数字电子电路的调试指的是对数字电路进行检测的工作,测验该电路的逻辑功能是否能够达到预先对电路的设计效果。想要使数字电子电路能够符合事先设计要求来进行准确工作,就应当对其进行一定的调试与调整处理。数字电子电路的调试与常规电子电路的调整存在着一定的相同之处,当然也存在有差异的地方,但同样具备调整常规电子电路的思想与思维方式,也就是“静态先动态后”的原则。倘若所调试的数字电子电路中具备多个模块单位,那么就应当先对子系统或者单位模块进行调试,接着再调试多个单元模块的电子电路,最后再来调试整个系统。 相似文献
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电子电路调试是电路设计中的重中之重,可提升电子电路的实效性.为实现电子电路设计质量的优化,文中讨论了基于电子电路设计基本原则对其常用调试方法和调试步骤,可以优化电子电路设计. 相似文献
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对电子电流进行调试,并且针对其故障进行分析处理对于电子电路理论设计的实践检验,让电子电路能够更加完善,性能更佳、使用更安全.电子电路的调试与故障处理给电子技术在生产生活与实践应用中发挥了十分重大的作用,并且给拓展了电子电路应用范围.现本文主要针对电子电路的调试与故障处理进行研究,以期可以为电子电路的发展提供借鉴与参考. 相似文献
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对于电子电路的设计和调试,应该坚持理论实践相结合的原则,确保电路设计的科学性,并且经过全面的调试确保电路更加完善。对于电子电路的各种器件来说,如果电路设计质量较差或者存在问题,就会导致电路安装完成后效果不尽如人意,并且在工作中也会出现各种误差,例如电阻误差、参数误差等,因此在电路设计和安装完成后必须进行调试,解决出现的问题,改正存在的缺陷,才能确保电子器件满足使用需求。 相似文献
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电子硬件测试技术是电子产品从研发到生产的必经的一个阶段,也是决定一件电子产品质量的重要环节,所以如果将电子产品的硬件测试技术发展的更加完善,更加专业也是很多电子产品生产企业追求的目标。本文从这一目标出发详细介绍了电子产品的硬件测试技术以及发展状况。 相似文献
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One of the most popular methods for reliability assessment of digital circuits is Fault Injection (FI) in which the behavior of the circuit is simulated in presence of faults. In this paper, we present a survey of FI techniques as well as classifying these techniques considering different aspects and criteria to bring out their similarities and differences. The goal of this paper is to help the researchers and reliable circuit designers in gaining insights into the state-of-art in FI techniques and motivate them to further improve these techniques for more efficient reliability evaluation of digital circuit designs of tomorrow. 相似文献
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基于OrCAD电路设计软件的高频电子线路仿真分析 总被引:2,自引:0,他引:2
本文基于OrCAD/Pspice电子线路计算机辅助分析设计软件以实现高频电子线路的综合电路分析仿真为目的,针对回路使用的信号频率比较高,电路实现的功能多、结构复杂,造成OrCAD设计软件在仿真过程时运算量大,电路调试过程变得复杂、电路的元器件参量优化难度大.通过采用复杂电路的仿真调试关联优化的方法对变容二极管调频与功率放大及发射电路的仿真过程进行分析,仿真效果表明,采用关联优化方法能有效提高优化设计效率。 相似文献
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A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach. 相似文献
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This paper presents a method for functional testing of analog circuits, on the basis of circuit sensitivities. The approach selects the minimum number of measurements that allows a precise prediction of a circuit's functional behavior. A criterion is applied to this predicted behavior to determine if the circuit functions according to specifications. The presented method combines a matrix decomposition technique (the singular value decomposition) with an iterative algorithm to select measurements. The number of measurements is determined on the basis of the desired precision of the response prediction and the influence of random measurement errors. Examples demonstrate that the resulting method tests the functional circuit behavior with a high precision, even in the presence of large measurement errors. 相似文献
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Stavros G. Stavrinides Kostas Papathanasiou Antonios N. Anagnostopoulos 《International Journal of Electronics》2013,100(2):233-247
In this paper, a new approach in identifying chaotic behaviour of nonlinear circuits is presented. This approach could be very useful to circuit designers, whether they pursue a chaotic behaviour or not. Simulation tools used for radio-frequency circuit design (Cadence SpectreRF), initially developed to characterise harmonic oscillators, are now utilised to detect chaotic behaviour, as well as routes to chaotic mode of operation. Specifically, Periodic Steady State Convergence Norm is used for the first time for chaos detection in circuits. The advantages of this method (especially in terms of simulation time) are presented, together with an example of detection of chaotic route to chaos in the case of a chaotic-operating Colpitts oscillator. 相似文献
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I. P. Litikov 《Journal of Electronic Testing》1991,1(4):301-304
Here we propose a new approach to the testing of digital devices, which can potentially save diagnostic hardware. An example is given for testing combinational devices. Estimates are given for reliability and hardware complexity, and an algorithm for designing operability tests is described. 相似文献
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This paper presents a novel technique for measuring the electrical characteristics of analogue circuits, based on measuring the temperature at the silicon surface close to the circuit under test. As a detailed example, the paper analyses how the gain of an amplifier can be observed through temperature measurements. Experimental results validate the feasibility of the technique. Simulated results show how this technique can be used to measure the bandwidth and central frequency of a 2.4 GHz low noise amplifier (LNA) designed in a 0.35 μm standard CMOS technology. 相似文献