复用NoC测试IP芯核测试存取链优化配置

论述了层次型IP芯核不同测试模式之间的约束关系,给出了层次型IP芯核的测试壳结构,提出了一种复用片上网络测试内嵌IP芯核的启发式测试存取链优化配置方法.该方法可有效减小测试数据分组数量和被测芯核的测试时间.使用片上网络测试平台,在测试基准电路集ITC'02中的基准电路p22810上进行了实验验证.     

一种适用于Chiplet测试的通用测试访问端口控制器电路设计

在后摩尔时代里，Chiplet是当前最火热的异构芯片集成技术，具有复杂的多芯粒堆叠结构等特点。为了解决Chiplet在不同堆叠结构中的芯粒绑定后测试问题，基于IEEE 1838标准协议，该文提出一种适用于Chiplet测试的通用测试访问端口控制器(UTAPC)电路。该电路在传统测试访问端口(TAP)控制器的基础上设计了Chiplet专用有限状态机(CDFSM)，增加了Chiplet测试路径配置寄存器和Chiplet测试接口电路。在CDFSM产生的配置寄存器控制信号作用下，通过Chiplet测试路径配置寄存器输出的配置信号来控制Chiplet测试接口电路以设置Chiplet的有效测试路径，实现跨层访问芯粒。仿真结果表明，所提UTAPC电路适用于任意堆叠结构的Chiplet的可测试性设计，可以有效地选择芯粒的测试，还节省了测试端口和测试时间资源并提升了测试效率。     

基于扫描链的FPGA可编程逻辑模块测试

随着FPGA规模的不断增大和结构的日益复杂,FPGA的测试也变得越来越困难.由此提出了一种可配置的FPGA芯核扫描链设计,并讨论了基于扫描链的可编程逻辑模块（Configuration Logic Blocks CLB）测试.提出的扫描设计可以通过配置调整扫描链的构成,从而能够处理多个寄存器故障,且在有寄存器故障发生时,重新配置后能继续用于芯片的测试.基于扫描链的CLB测试,以扫描链中的寄存器作为CLB测试的可控制点和可观测点,降低了对连线资源的需求,可以对所有的CLB并行测试,在故障测试的过程中实现故障CLB的定位,与其它方法相比,所需配置次数减少50%以上.     

基于差值二次分配的扫描链平衡算法

 IP核的测试时间与其加载测试封装后的最大输入/输出扫描链长度有直接关系,为了降低测试成本,减少测试时间,必须对IP核内的扫描链进行平衡设计.最为经典的扫描链平衡方法是BFD(Best Fit Decrease)方法,它具有实现简单、算法复杂度低等优点,但是其分配的结果尚有待提高之处.本文提出一种基于差值的二次分配的扫描链平衡方法,其主要思想是选择IP核内部的某一条扫描链作为基准扫描链,将其长度记为L,将所有长度超过L的扫描链与之做差,并将差值记为di.在第一次分配中,只将长度大于L的扫描链按照长度为L的基准扫描链进行分配;然后将长度小于L的扫描链与差值di重新排序后,按照从大到小的顺序,依次将其放置在可以放置的最小的测试封装扫描链上进行第二次分配.该方法简单易实现,通过在ITC'02 SOC标准测试集上实验,数据表明,基于差值二次分配的扫描链平衡方法与现有方法相比,能得到更好的平衡结果.     

SOC的低功耗快速测试

SOC由多个芯核组成,它的测试可以分为系统级和芯核级来解决,也可以从电路结构和测试算法两个方面来进行.测试时间长,测试数据量大,测试功耗高是系统芯片测试的难题.解决这些问题的途径主要有:基于软件和硬件协同测试的方法;对测试向量进行处理的方法;在测试电路中使用翻转较少的触发器的DFT结构;合理的划分片上的可测试资源.还给出了尚需进行的研究工作.     

基于外壳架构与测试访问机制的数字芯核可测试性设计

深亚徽米技术的应用以及芯核的嵌入性特点.使传统的测试方法不再能满足芯核测试的需要.IEEEStdl 500针对此问题提出了芯核的可测试性设计方案——外壳架构和测试访问机制.基于IEEE Stdl 500.以74373与741 38软梭为例,提出数字芯梭可测试性设计的方法,并通过多种指令仿真验证了设计的合理性;设计的TAM控制器复用JTAC-端口,节约了测试端口资源.提供了测试效率.     

片上网络路由器的测试及其外壳旁路故障的诊断

目前采用IEEE 1500测试外壳的方法可以一定程度上解决NoC(Netword on Chip)路由器测试的问题,但当测试外壳的旁路出现一个以上的故障时,很可能导致一整条扫描链上的NoC路由器测试失败.针对该问题,本文通过提出一个深度优先最短路径算法得到从固定的扫描输入端到扫描输出端的最短路径,并通过提出的递归划分逐步求精法对路径进行筛选分块排序,构造多条扫描测试链将整个网络中的路由器分开测试.本文给出了测试外壳旁路故障的诊断和容错方法,使用节点分类测试方法实现对NoC路由器旁路故障的定位,并通过本文提出的测试外壳结构实现对故障旁路的容错.     

单链扫描可测性设计中存储元件的排序

本文提出了扫描设计中存储元件在扫描链中的最优排序方法。采用交迭测试体制和区间法能快速求出最优解。对于确定的测试向量集，用该方法构造的扫描链能使电路总的测试时间最少。     

动态向量调整的多扫描链测试数据压缩

 由于多扫描链测试方案能够提高测试进度,更适合大规模集成电路的测试,因此提出了一种应用于多扫描链的测试数据压缩方案.该方案引入循环移位处理模式,动态调整向量,能够保留向量中无关位,增加向量的外延,从而提高向量间的相容性和反向相容性;同时,该方案还能够采用一种有效的参考向量更替技术,进一步提高向量间的相关性,减少编码位数.另外,该方案能够利用已有的移位寄存器,减少不必要的硬件开销.实验结果表明所提方案在保持多扫描链测试优势的前提下能够进一步提高测试数据压缩率,满足确定性测试和混合内建自测试.     

全扫描设计中多扫描链的构造

本文在交迭测试体系 的基础上提出了一种多扫描链的区间构造法,对于确定的测试向量集能够显著地减少测试应用时间.该构造方法根据规定的扫描链数,通过求解线性规划问题的方法确定扫描寄存器在扫描链上的优化的分布区间,从而构造多扫描链,最后根据对多扫描链进行连线复杂度的定性分析,求得连线复杂度最低的多扫描链的最优构造.     

Test-access mechanism optimization for core-based three-dimensional SOCs

Embedded cores in a core-based system-on-chip (SOC) are not easily accessible via chip I/O pins. Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) have been proposed for the testing of embedded cores in a core-based SOC in a modular fashion. We show that such a modular testing approach can also be used for emerging three-dimensional integrated circuits based on through-silicon vias (TSVs). Core-based SOCs based on 3D IC technology are being advocated as a means to continue technology scaling and overcome interconnect-related bottlenecks. We present an optimization technique for minimizing the post-bond test time for 3D core-based SOCs under constraints on the number of TSVs, the TAM bitwidth, and thermal limits. The proposed optimization method is based on a combination of integer linear programming, LP-relaxation, and randomized rounding. It considers the Test Bus and TestRail architectures, and incorporates wire-length constraints in test-access optimization. Simulation results are presented for the ITC 02 SOC Test Benchmarks and the test times are compared to that obtained when methods developed earlier for two-dimensional ICs are applied to 3D ICs. The test time dependence on various 3D parameters (e.g. 3D placement, the number of layers, thermal constraints, and the number of TSVs) is also studied.     

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows pre-bond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1149.1 or IEEE Std 1500. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies.     

一种改进的层次化SOCs并行测试封装扫描单元

 测试封装是实现SOC内部IP核可测性和可控性的关键,而扫描单元是测试封装最重要的组成部分.然而传统的测试封装扫描单元在应用于层次化SOCs测试时存在很多缺点,无法保证内部IP核的完全并行测试,并且在测试的安全性,功耗等方面表现出很大问题.本文提出一种改进的层次化SOCs测试封装扫描单元结构,能够有效解决上述问题,该结构的主要思想是对现有的扫描单元进行改进,实现并行测试的同时,通过在适当的位置增加一个传输门,阻止无序的数据在非测试时段进入IP核,使得IP核处于休眠状态,保证了测试的安全性,实现了测试时的低功耗.最后将这种方法应用在一个工业上的层次化SOCs,实验分析表明,改进的测试封装扫描单元比现有扫描单元在增加较小硬件开销的前提下,在并行测试、低功耗、测试安全性和测试覆盖率方面有着明显的优势.     

Wrapper design for multifrequency IP cores

This paper addresses the testability problems raised by intellectual property cores with multiple clock domains. The proposed solution is based on a novel core wrapper architecture and a new wrapper design algorithm. It is shown how multifrequency at-speed test response capture can be achieved via the design of capture windows without any structural modifications to the logic within the embedded core. The new features in the core wrapper architecture, which introduce limited hardware overhead, can also synchronize the external tester channels with the core's internal scan chains in the shift mode. Thus, the wrapper implementation space can be explored in order to efficiently utilize the available tester bandwidth while meeting the constraints on the maximum internal shift frequency that guarantees low testing time within the given power ratings. Using experimental data, the benefits of the proposed solution are demonstrated by analyzing the tradeoffs between the number of tester channels, testing time, area overhead, and power dissipation.     

基于安全控制边界单元的IP核测试封装方法

为了解决测试信息传递的问题,IEEE组织推出了IEEE1500 IP(Intellectual Property)核测试封装标准以标准化口核测试接口.然而该标准给出的典型测试封装存在由测试数据扫描移人造成的不安全隐患.本文提出了一种基于安全控制边界单元的IP核测试封装方法.这种方法的核心思想是在典型的测试封装边界单元的...     

IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs

A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC’02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10–50%.     

A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling

The increasing test application times required for testing system-on-chips (SOCs) is a problem that leads to higher costs. For modular core based SOCs it is possibly to employ a concurrent test scheme in order to lower the test application times. To allow each core to be tested as a separate unit, a wrapper is inserted for each core, the scan chains at each core are configured into a fixed number of wrapper chains, and the wrapper chains are connected to the test access mechanism. A problem with concurrent testing is that it leads to higher power consumption as several cores are active at a time. Power consumption above the specified limit of a core or above the limit of the system will cause damage and must be avoided. The power consumption must be controlled both at core level as well as on system level. In this paper, we propose a reconfigurable power conscious core wrapper that we include in a preemptive power constrained test scheduling algorithm. The advantages with the wrapper are that the number of wrapper chains at each core can dynamically be changed during test application and the possibility, through clock gating, to select the appropriate test power consumption for each core. The scheduling technique produces optimal solutions in respect to test time and selects wrapper configurations in a systematic manner while ensuring the power limits at core level and system level are not violated. The wrapper configurations are selected such that the number of wrapper configurations as well as the number of wrapper chains at each wrapper are minimized, which minimizes the wrapper logic as well as the total TAM routing. We have implemented the technique and the experimental results show the efficiency of our approach. The research is supported by the Swedish Foundation on Strategic Research (SFS) under the Strategic Integrated Electronic Systems Research (STRINGENT) program.     

基于TSV绑定的三维芯片测试优化策略

本文提出一种三维片上系统(3D SoC)的测试策略,针对硅通孔(TSV,Through Silicon Vias)互连技术的3D SoC绑定中和绑定后的测试进行优化,由于测试时间和用于测试的TSV数目都会对最终的测试成本产生很大的影响,本文的优化策略在有效降低测试时间的同时,还可以控制测试用的TSV数目,从而降低了测试成本.实验结果表明,本文的测试优化策略与同类仅考虑降低测试时间的策略相比,可以进一步降低约20%的测试成本.