一种深亚微米PDSOI NMOS总剂量辐照模型

在以往的大部分总剂量辐照模型中,人们只研究体偏为0V时的阈值电压漂移以及迁移率退化。然而,测试数据表明总剂量辐照效应与体偏紧密相关,为了模拟体偏对总剂量效应的影响,本文提出了一个宏模型,宏模型包括阈值电压、迁移率、以及漏电在不同体偏下随总剂量的变化。基于中国科学院微电子研究所开发的0.35µm PDSOI工艺的NMOS测试数据很好的验证了此模型,尤其是漏电部分。     

A total dose radiation model for deep submicron PDSOI NMOS

In most of the total dose radiation models,the drift of the threshold voltage and the degradation of the carrier mobility were only studied when the bulk potential is zero.However,the measured data indicate that the total dose effect is closely related to the bulk potential.In order to model the influence of the bulk potential on the total dose effect,we proposed a macro model.The change of the threshold voltage,carrier mobility and leakage current with different bulk potentials were all modeled in this model,and the model is well verified by the measured data based on the 0.35μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences,especially the part of the leakage current.     

An innovative interconnect structure with improved Elmore delay estimation model for deep submicron technology

With advancements in technology, size and speed have been the important facet in VLSI interconnects. The channel length of the device reduces to tens of nanometers, as the technology is transferring to the deep submicron level. This leads to the requirement of long interconnects in VLSI chips. Interconnects are known as the basic building block that can vary from size to size. They provide a connection between two or more blocks and have scaling problems that an IC designer faces while designing. As scaling increases, the impact of interconnect in the VLSI circuits became even more important. It controls all the important electrical characteristics on the chip. With scale-down technology, interconnects not only become closer with each other but their dimensions also change which can directly impact the circuit parameters. Certain RC models have already been defined to control these parameters but in this paper, authors have proposed a new improved Elmore delay estimation model (RC) to reduce delay and power consumption in interconnect circuits. An optimized Elmore delay calculation was performed for uniform and non-uniform wires to reduce the time constant of the interconnect circuits. Further, the proposed model is estimated and verified theoretically. A new improved RC model is compared to the designed π-model that shows remarkable results. We also observed the linear relationship of power consumption and delay for both the RC models and found that in π-model, upon decreasing the length of wire the power first increases then decreases but in the proposed model, the power first increases then remain constant and then further increases upon increasing the length of wire. Our proposed model shows the remarkable values as the average percentage improvement of power is 75.167% and delay as 74.714% is achieved using a uniform distribution.

     

A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM

In this paper, the effect of the nonself-aligned process on the performance variation of a bottom-gate metal oxide semiconductor (MOS) transistor is discussed using a device simulator. The simulation results predict that the nonself-aligned bottom-gate MOS transistor cannot be scaled into the deep submicron regions. A simple fully self-aligned bottom-gate (FSABG) metal oxide semiconductor field effect transistor (MOSFET) technology is then proposed and developed. A new technique for forming thermal oxide on poly-Si serving as the bottom-gate dielectric is also investigated. It is found that the quality of the oxide on the poly-Si recrystallized by the metal induced uni-lateral crystallization (MIUC) is much higher than that by the solid phase crystallization (SPC). Deep submicron fully self-aligned bottom-gate pMOS transistors are fabricated successfully using the proposed technology. The experimentally measured results indicate the device performances depend strongly on the channel-width, and get comparable to that of a single crystal MOSFET if the channel width is less than 0.5/spl mu/m. The effects of the channel width on the device performances are discussed. In addition, the experimental results also confirm that the proposed technology has a good control of the channel film thickness.     

Influence of gate length on ESD-performance for deep submicron CMOS technology

ESD-performance of grounded-gate nMOS protection structures has been observed for a standard 0.25 μm CMOS epitaxial layer based technology. The shortest gate lengths show unexpectedly lower ESD-thresholds, leading to an optimum performance for longer gate length devices attributed to the trade off between power dissipation and melt volume of the parasitic bipolar.     

Interconnect noise analysis and optimization in deep submicron technology

The migration to using ultra deep submicron (UDSM) process, 0.25 /spl mu/m or below, necessitates new design methodologies and EDA tools to address the new design challenges. One of the main challenges is noise. All different types of deep submicron such as cross talk, leakage, supply noise and process variations are obstacles in the way of achieving the desired level of noise immunity without giving up the improvement achieved in performance and energy efficiency. This article describes research directions and various levels of design abstraction to handle the interconnect challenges. These directions include approaches to adopt new analytical methods for interconnects, physical design levels and finally ways to face these challenges early in a higher level of the design process.     

Analytical drain thermal noise current model valid for deep submicron MOSFETs

In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.     

An analytical model with flexible accuracy for deep submicron DCVSL cells

Differential cascoded voltage switch logic (DCVSL) cells are among the best candidates of circuit designers for a wide range of applications due to advantages such as low input capacitance, high switching speed, small area and noise-immunity; nevertheless, a proper model has not yet been developed to analyse them. This paper analyses deep submicron DCVSL cells based on a flexible accuracy-simplicity trade-off including the following key features: (1) the model is capable of producing closed-form expressions with an acceptable accuracy; (2) model equations can be solved numerically to offer higher accuracy; (3) the short-circuit currents occurring in high-low/low-high transitions are accounted in analysis and (4) the changes in the operating modes of transistors during transitions together with an efficient submicron I-V model, which incorporates the most important non-ideal short-channel effects, are considered. The accuracy of the proposed model is validated in IBM 0.13 µm CMOS technology through comparisons with the accurate physically based BSIM3 model. The maximum error caused by analytical solutions is below 10%, while this amount is below 7% for numerical solutions.     

An analytical thermal noise model of deep submicron MOSFET's

An analytical model for circuit simulation to describe the channel thermal noise in MOSFET's for all channel length down to deep submicron is presented and verified by measurements. Contrary to the thermal equilibrium assumption, this model includes the influence of the increasing electrical field with downscaling on the channel carrier (electron, hole) equivalent noise temperature. If not taken into account, simulation errors of up to 100% and more in the thermal noise of half micron transistors and below occur     

Reliability challenges for deep submicron interconnects

Deep submicron interconnects (leads, contacts and vias) are rapidly becoming one of the major reliability challenges as ULSI devices continue to be scaled. With 0.5um feature sizes now common, trying to balance reliability and performance requirements is increasing difficult as we move toward <0.25um. By the end of the decade, current density in metal leads will be >0.5 Ma/cm2 and single 0.20–0.25um contacts and vias will be required to safely carry 1–2ma of current. This increases electromigration concerns, with vias generally now being the weakest link in a reliable ULSI multilevel-metal system.     

Crosstalk effects in mixed-signal ICs in deep submicron digital CMOS technology

This paper illustrates the crosstalk phenomenon and its impact on the design of mixed analog/digital circuits with high accuracy specifications. Generation of digital disturbs, propagation through the substrate, and effects on analog devices are considered, with particular emphasis on integrated circuits realized on heavily doped substrate, where traditional shielding is less effective. Techniques to reduce analog/digital crosstalk are reviewed and discussed. A simple modeling approach is presented, suitable for the analysis of crosstalk effects using a conventional electrical simulator (SPICE). Experimental results on a test chip are presented to validate the modeling approach.     

A new field dependent mobility model for high frequency channel thermal noise of deep submicron RFCMOS

In this paper, a new field dependent effective mobility model including the drain-induced vertical field effect (DIVF) is presented to calculate the channel thermal noise of short channel MOSFETs operating at high frequencies. Based on the new channel thermal noise model, the simulated channel thermal noise spectral densities have been compared to the channel thermal noise directly extracted from noise measurements on devices fabricated using GLOBALFOUNDRIES’ 0.13 μm RFCMOS technology. The comparison has been done across different channel length, finger width and number of finger for different frequencies, gate biases and drain biases. Excellent agreement between simulated and extracted noise data has shown that the proposed model is scalable over different dimensions and operating conditions. The proposed model is simple and can be easily implemented in a circuit simulation environment.     

Prognostic methodology for deep submicron semiconductor failuremodes

Semiconductor reliability issues are beginning to emerge as a major impediment to long term reliability of critical systems such as Internet routers, ATM machines, and Automotive/Aerospace fly-by-wire systems. Semiconductors have certain defined failure modes that can contribute to end-of life failures. These modes include time-dependent dielectric breakdown of the gate oxide (TDDB), hot carrier damage, and metal migration. All of these common failure modes are far worse at geometries below 0.25 μm. Fortunately, there are methods proposed that counteract these common failure modes. This paper surveys the problems involved, and recommends a methodology for the inclusion of pre-calibrated prognostic cells that can be co-located with a host circuit to provide an “early-warning” of a system failure, so that appropriate corrective action can be taken     

A novel self-aligned T-shaped gate process for deep submicron SiMOSFET's fabrication

T-shaped gate electrode is highly desired for high-speed FET fabrication since it can significantly reduce the gate resistance. In this study, we propose and demonstrate a self-aligned method of forming T-shaped gate which is suitable for ULSI Si-MOSFET's fabrication. This method employs CMP planarization, BOE selective etching and poly-Si sidewall spacer techniques to form the T-shaped poly-Si gate structure. Ti and Co silicidation were also incorporated to demonstrate the effectiveness of this process. Our experimental results indicate that the proposed process not only reduces the parasitic gate resistance, but also improves the thermal stability of the gate structure     

漏及衬底偏压对深亚微米工艺器件总剂量效应的影响

本文对采用0.18?m工艺制造的NMOS器件辐射总剂量效应进行了研究。对晶体管进行了不同剂量的₆₀Co辐射实验,同时测试了辐照前后晶体管电学参数随漏、衬底偏压的变化的规律。采用STI寄生晶体管模型来解释晶体管的关态漏电流及阈值电压漂移性质。3D器件仿真验证了模型的准确性。     

Leakage scaling in deep submicron CMOS for SoC

In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25°C to 125°C) of the four components of off-state drain leakage (I_off ) (i.e. subthreshold leakage (I_sub), gate edge-direct-tunneling leakage (I_EDT), gate-induced drain-leakage (I_GIDL), and bulk band-to-band-tunneling leakage (I_B-BTBT)). In addition, the high temperature characteristics of I_off with reverse body bias (V_B) for the further reduction of the standby leakage are also demonstrated. The discussion is based on the data measured from three CMOS logic technologies (i.e., low-voltage and high performance (LV), low-power (LP), and ultra-low-power (ULP)) and three generations (0.18 μm, 0.15 μm, and 0.13 μm). Experiments show that the optimum V_B, which minimizes I_off, is a function of temperature. The experiments also show that for CMOS logic technologies of the next generations, it is important to control I_B-BTBT and I_GIDL by reducing effective doping concentration and doping gradient. It seems that in order to conform on-state gate leakage (I_G-on) and I_EDT specifications and to retain a 10-20% performance improvement at the same time, it is indispensable to use high-quality and high-dielectric-constant materials to reduce effective oxide thickness (EOT). The role of each leakage component in SRAM standby current (I_SB) is also analyzed     

A deep submicron CMOS process compatible suspending high-Q inductor

A novel high-Q on-chip inductor structure called suspending inductor is developed to improve the characteristics of the conventional on-chip spiral inductor. The suspending inductor employs the air gap and is supported by a set of novel metal pillars to suppress the capacitance from the metal layer to the substrate. The measured maximum quality factor of the suspending inductor is improved from 4.8 to 6.3 in comparison to the conventional spiral inductor. Furthermore, the frequency at maximum quality factor is raised from 1.5-2 GHz     

A single-V/sub t/ low-leakage gated-ground cache for deep submicron

In this paper, we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high-performance cache memories using single V/sub t/ (transistor threshold voltage) process. We utilize the concept of gated-ground (nMOS transistor inserted between ground line and SRAM cell) to achieve a reduction in leakage energy without significantly affecting performance. Experimental results on gated-ground caches show that data is retained (DRG-Cache) even if the memory is put in the standby mode of operation. Data is restored when the gated-ground transistor is turned on. Turning off the gated-ground transistor in turn gives a large reduction in leakage power. This technique requires no extra circuitry; the row decoder itself can be used to control the gated-ground transistor. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy, such as the L1, L2, or L3 caches. We fabricated a test chip in TSMC 0.25-/spl mu/m technology to show the data retention capability and the cell stability of the DRG-Cache. Our simulation results on 100-nm and 70-nm processes (Berkeley Predictive Technology Model) show 16.5% and 27% reduction in consumed energy in L1 cache and 50% and 47% reduction in L2 cache, respectively, with less than 5% impact on execution time and within 4% increase in area overhead.     

A model for anomalous short-channel behavior in submicron MOSFETs

Experimental data and simulation results for submicron MOSFETs are reported and used to support a physical explanation for two important anomalies in the dependence of device threshold voltage on channel length. They are the widely observed increase in threshold voltage with decreasing channel length (roll-up), and the more recent observation that the ultimate threshold voltage decrease (roll-off) occurs at a rate which is far in excess of that which can be explained with conventional models of laterally uniform channel doping. A model that attributes roll-up as well as roll-off to lateral redistribution of doping near the source and drain junctions is proposed. This lateral redistribution is caused by crystal defects formed during post-source/drain-implant anneal. The resulting profile consists of an enhancement of background doping adjacent to the junction edge, bounded by a depression of the doping farther into the channel     

Design and fabrication of deep submicron CMOS technology compatible suspended high-Q spiral inductors

In this paper, deep submicron complementary metal-oxide-semiconductor (CMOS) process compatible high-Q suspended spiral on-chip inductors were designed and fabricated. In the design, the electromagnetic solver, SONNET, and the finite element program, ANSYS, were used for electrical characteristics, maximum endurable impact force, and thermal conduction simulations, respectively. Based on the design, suspended spiral inductors with different air cavity structures, i.e., diamond opening, circle opening, triangle opening, and full suspended with pillar supports were developed for various applications. Among these structures, the suspended inductor with pillar support possesses the highest Q/sub max/ (maximum of quality factor) of 6.6 at 2 GHz, the least effective dielectric constant of 1.06, and the lowest endurable impact force 0.184 Newton. On the other hand, the spiral inductor with diamond opening has a lowest Q/sub max/ of 4.3, the largest effective dielectric constant of 3.44 and highest endurable impact force 4 Newton. The former is suitable for station telecommunication applications in which the mechanical vibration is not a serious concern, while the latter can be used for mobile telecommunication applications subject to strong mechanical vibrations. Additionally, the conventional on-chip spiral inductor embraced by SiO/sub 2/ with a dielectric constant of 4 was prepared for comparison and found its Q/sub max/ is 3.8 at 1.2 GHz.