A 4-Mbit DRAM with half-internal-voltage bit-line precharge

A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-/spl mu/m minimum design rule. As a result, a 4M word/spl times/1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-/spl mu/m/SUP 2/ storage cells.     

A 4-Mbit CMOS EPROM

A high-density (512K-word/spl times/8-b) erasable programmable read-only memory (EPROM) has been designed and fabricated by using 0.8-/spl mu/m n-well CMOS technology. A novel chip layout and a sense-amplifier circuit produce a 120-ns access time and a 4-mA operational supply current. The interpoly dielectric, composed of a triple-layer structure, realizes a 10-/spl mu/s/byte fast programming time, in spite of scaling the programming voltage V/SUB PP/ from 12.5 V for a 1-Mb EPROM to 10.5 V for this 4-Mb EPROM. To meet the increasing demand for a one-time programmable (OTP) ROM, a circuit is implemented to monitor the access time after the assembly. A novel redundancy scheme is incorporated to reduce additional tests after the laser fuse programming. Cell size and chip size are 3.1/spl times/2.9 /spl mu/m/SUP 2/ and 5.86/spl times/14.92 mm/SUP 2/, respectively.     

A 50-/spl mu/A standby 1M/spl times/1/256K/spl times/4 CMOS DRAM with high-speed sense amplifier

A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.     

A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifier

A 4-Mb word/spl times/1-b/1-Mb word/spl times/4-b CMOS DRAM characterized by a twisted driveline sense-amplifier (TDSA) scheme and a multiphase drive circuit which enable faster access time and a smaller peak power supply current, respectively, is described. The implementation of an initialize mode with CAS-before-RAS (CBR) logic control, which reduces the memory-chip initialization time by almost a thousand times, is also discussed. The chip measures 6.38/spl times/17.38 mm/SUP 2/ and has been fabricated by using double-well CMOS technology with a minimum design rule of 0.8 /spl mu/m. A typical access time of 65 ns and a peak power supply current of less then 150 mA have been obtained.     

A 60-ns 4-Mbit CMOS DRAM with built-in selftest function

A 4-Mb CMOS DRAM measuring 6.9/spl times/16.11 mm/SUP 2/ has been fabricated using a 0.9-/spl mu/m twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5/spl times/5.5 /spl mu/m/SUP 2/ each, are incorporated in a p-well. A novel built-in selftest (BIST) function which enables a simultaneous and automatic test of all the memory devices on a board is introduced to reduce the RAM testing time in a system. This function is effective for system maintenance and a daily start-up test even in a relatively small system. A high-speed low-power 4-Mb CMOS DRAM with 60-ns access time, 50-mA active current, and 200-/spl mu/A standby current is realized by widening the DQ line bus which connects the sense amplifiers with DQ buffers, thereby reducing the parasitic capacitance of the DQ lines.     

A GaAs 16 K SRAM with a single 1-V supply

A GaAs 4 K/spl times/4-b static random access memory (SRAM) with 11-ns access time and 1-W power dissipation is described. The device is fabricated using 1.0-/spl mu/m WSi/SUB x/ selfaligned gate metal semiconductor FET (MESFET) and double-level interconnection technology. Optimization of fan-out and adoption of an address precoder circuit enable both fast access time and low power dissipation. The SRAM operates with a single 1.0-V supply.     

DRAM macros for ASIC chips

DRAM macros in 4-Mb (0.8-μm) and 16-Mb (0.5-μm) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT cell) DRAM products. It is shown that the trench cells with capacitor plates by the grounded substrate are ideal structures as embedded DRAM's. The trench cells built entirely under the silicon surface allow cost effective DRAM and CMOS logic merged process technologies. In the 0.8-μm rule, the DRAM macro has a 32-K×9-b configuration in a silicon area of 1.7×5.0 mm² . It achieves a 27-ns access and a 50-ns cycle times. The other DRAM macro in the 0.5-μm technology is organized in 64 K×18 b. It has a macro area of 2.1×4.9 mm and demonstrated a 23-ns access and a 40-ns cycle times. Small densities and multiple bit data configurations provide a flexibility to ASIC designs and a wide variety of application capabilities. Multiple uses of the DRAM macros bring significant performance leverages to ASIC chips because of the wide data bus and the fast access and cycle times. A data rate more than 1.3 Gb/s is possible by a single chip. Some examples of actual DRAM macro embedded ASIC chips are shown     

An experimental 1-Mbit BiCMOS DRAM

Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1.3 /spl mu/m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5.0/spl times/14.9 mm/SUP 2/.     

A 1-Mbit CMOS DRAM with fast page mode and static column mode

A 1-Mb words/spl times/1-bit CMOS dynamic RAM fabricated with an advanced n-well CMOS technology is described. More than 2.2 million devices are integrated on a 62.5 mm/SUP 2/ silicon chip by utilizing an n-channel memory cell of triple-level poly Si structure and a 1.2-/spl mu/m feature size VLSI process. Novel CMOS circuit design techniques such as the half V/SUB cc/ bitline precharge scheme are successfully applied to realize the excellent performance combination of high-speed operation and low-power dissipation. The CMOS peripheral circuitry is capable of the new operating functions, fast page mode, or static column mode with metal mask options. The typical RAS access time is 56 ns, the active current is 30 mA at a 190-ns cycle time, and the standby current is 0.2 mA.     

A 4-Mbit DRAM with trench-transistor cell

An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.     

An experimental 4-Mbit CMOS DRAM

A 4-Mb dynamic RAM has been designed and fabricated using 1.0-/spl mu/m twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high /spl alpha/-particle immunity was achieved with this structure. One cell measures 3.0/spl times/5.8 /spl mu/m/SUP 2/ yielding a chip size of 7.84/spl times/17.48 mm/SUP 2/. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static-column-mode and fast-age-mode operation. The chip is usable as /spl times/1 or /spl times/4 organizations with a bonding option. Using an external 5-V power supply, the row-address-strobe access time is 80 ns at room temperature. The typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.     

A 1-Mbit CMOS dynamic RAM with design-for test functions

A 1-Mb CMOS DRAM measuring 4.3/spl times/11.7 mm/SUP 2/ (50.32 mm/SUP 2/) has been fabricated using 1.0-/spl mu/m CMOS double-poly single-metal process technology. Both moat and second-level poly are clad to reduce circuit propagation delays. The chip incorporates two modes of 8-bit parallel READ/WRITE, as well as additional functions for test-time reduction. Eight 1-Mb family members can be produced by metal mask selection. The device uses static column circuitry along with two-stage intermediate output buffers to achieve a typical column address access time of 20 ns.     

A 128K word/spl times/8 bit dynamic RAM

A 1-Mb DRAM with 128K/spl times/8 bit organization is described. In designing the circuit, half V/SUB cc/ bit line precharge with dummy reverse circuits was adopted for noise reduction. The noise is estimated using a three-dimensional capacitance calculation. In realizing the chip, a 1-/spl mu/m NMOS process with double-level aluminum wiring was used.     

A 35 ns 2K /spl times/ 8 HMOS static RAM

This paper describes the circuit design and process techniques used to produce a 35-ns 2K /spl times/ 8 HMOS static RAM aimed at future high-end microprocessor applications. The circuit design uses predecoding of the row and column decoder/driver circuits to reduce active power, address-transition detection schemes to equalize internal nodes, and dynamic depletion-mode configurations for increased drive and speed. The technology is 2.5-3.0-/spl mu/m design rule HMOS employing an L/SUB eff/ of 1.7 /spl mu/m, t/SUB ox/=400 /spl Aring/, double-poly resistor loads, RIE and plasma etching, and wafer-stepper lithography. Using these techniques an access time of 35 ns, dc active power of 65 mA, standby power of 14 mA, and die size of 37.5K mil/SUP 2/ has been achieved. The cell size is 728 /spl mu/m/SUP 2/.     

An 18 ns CMOS/SOS 4K static RAM

A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of the rather conservative 3.5 /spl mu/m design rule except for the 2 /spl mu/m gate length, the cell size of 36/spl times/36 /spl mu/m, the die size of 3.11/spl times/4.07 mm, and the typical read access and cycle time of 18 ns are achieved. The active and standby power dissipation are 200 mW and 50 /spl mu/W, respectively.     

A 288K CMOS pseudostatic RAM

A 288-kb pseudostatic RAM with high density and ease of use has been fabricated using polycide-gate n-well CMOS technology. For high speed and low power dissipation, a half-V/SUB cc/ precharging scheme, with CMOS back biased to V/SUB BB/, was used. For easier use, an address transition detector, plus auto-refresh and self-refresh, were adopted. Organized as 32K/spl times/9 bits, the RAM occupies an area of 55 mm/SUP 2/ and has a cell size of 6.8/spl times/13.6 /spl mu/m/SUP 2/, which was achieved using the 2-/spl mu/m design rule. A typical address access time is 125 ns, and the operating current is 60 mA at a 125-ns cycle time. Standby power is 2 mA.     

A low-power sub 100 ns 256K bit dynamic RAM

A 256K-word /spl times/ 1-bit NMOS dynamic RAM using 2-/spl mu/m design rules and MoSi/SUB 2/ gate technology is described. A marked low-power dissipation of 170 mW (5 V V/SUB cc/, 260-ns cycle time) has been achieved by using a partial activation scheme. Optimized circuits exhibit a typical CAS access time of 34 ns. For the purpose of optimizing circuit parameters, an electron beam tester was successfully applied to observe the internal timing of real chips. Laser repairable redundancy with four spare rows and four spare columns is implemented for yield improvement.     

A high performance 1 Mbit EPROM

A high-performance 1-Mb EPROM has been developed by utilizing advanced 1.2-/spl mu/m minimum design rule technology. The device technology used is n-channel E/D MOS. The memory cell size is 5.5/spl times/7.5 /spl mu/m and the die size is 9.4/spl times/7.2 mm. The word organization is changeable between 64K words/spl times/16 bits and 128K words/spl times/8 bits. The active power dissipation is 500 mW and the standby power dissipation is 150 mW. The access time is typically 200 ns. The programming voltage is 12-14 V and the programming pulse width is typically 1 ms/word. In order to realize such a high-density, high-speed, low power 1-Mb EPROM, 1.2-/spl mu/m minimum patterning process technology, a high-speed sense amplifier, and a high-speed decoder are used.     

A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM

A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 /spl mu/m/SUP 2/, and a chip size of 20 mm/SUP 2/ has been developed. High performance is achieved using a high-speed Schottky barrier diode decoder with a pull-up circuit and a double-stage discharge circuit for a word-line driver. Small cell size is obtained using ultra-thin Ta/SUB 2/O/SUB 5/ film capacitors and 1-/spl mu/m U-groove isolation technology. An access time of 3.5 ns in this 16-kb bipolar RAM is equivalent to an effective access time of 2.5 ns at the system level, due to an on-chip address buffer and latch.     

A submicron 1 Mbit dynamic RAM with a 4-bit-at-a-time built-in ECC circuit

A submicron CMOS 1-Mb RAM with a built-in error checking and correcting (ECC) circuit is described. An advanced bidirectional parity code with a self-checking function is proposed to reduce the soft error rate. A distributed sense circuit makes it possible to implement a small memory cell size of 20 /spl mu/m/SUP 2/ in combination with a trench capacitor technique. The 1M word/spl times/1 bit device was fabricated on a 6.4/spl times/8.2 mm chip. The additional 98-kb parity cells and the built-in ECC circuit occupy about 12% of the whole chip area. The measured access time is 140 ns, including 20 ns ECC operation.