Minimizing Phase Noise Variation in CMOS Ring Oscillators

The variation of phase noise across the frequency of operation of a CMOS ring oscillator is described analytically. The delay element of the ring oscillator considered comprises of a source-coupled differential pair with an active load element. In this circuit topology where the frequency of oscillation is varied by changing the resistance of the load, theory derived in this work predicts that phase noise will remain constant if constant output swing is maintained. Such an oscillator is designed in a 0.5 m CMOS process and the simulation results verify the theoretical analysis. Consequently, an oscillator design methodology is provided that dramatically reduces the phase noise optimization problem to just one frequency within the oscillator's output frequency range.     

Temperature-compensated CMOS ring oscillator for power-management circuits

The design of a temperature-compensated CMOS ring oscillator is introduced. The concept is to make use of a linear, positively or negatively temperature-sloped supply voltage to power-up the ring oscillator. Experimental results show that the oscillation frequency remains fairly constant using the proposed scheme.     

粗调和细调相结合的标准CMOS低噪声环形压控振荡器

本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz～1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。     

一款用于LED驱动芯片的CMOS振荡器

研究一款适用于LED驱动芯片的CMOS振荡器电路.其工作原理是在环路振荡器中加入恒定电流源,以恒定电流对电容充电、MOS管对电容快速放电以产生锯齿波再经锁存器产生周期脉冲信号.与传统的环路振荡器相比,此电路的优点是振荡频率精确、波形稳定,振荡频率在一定的电源电压范围内对电源电压变化不敏感.此振荡器电路已经成功应用于一款LED驱动芯片中.     

CMOS ring VCO for UHF RFID readers

A complementary metal oxide semiconductor (CMOS) voltage controlled ring oscillator for ultra high frequency (UHF) radio frequency identification (RFID) readers has been realized and characterized. Fabricated in charter 0.35 μm CMOS process, the total chip size is 0.47×0.67 mm2. While excluding the pads, the core area is only 0.15×0.2 mm2. At a supply voltage of 3.3 V, the measured power consumption is 66 mW including the output buffer for 50 Ω testing load. This proposed voltage-controlled ring oscillator exhibits a low phase noise of - 116 dBc/Hz at 10 MHz offset from the center frequency of 922.5 MHz and a lower tuning gain through the use of coarse/fine frequency control.     

一种频率可调CMOS环形振荡器的分析与设计

给出了一个采用0．6um CMOS工艺设计的改进结构环形振荡器,电路由RC充放电回路、施密特单元以及反相延时单元组成,结构简单,工作频率受集成电路工艺参数影响小。该电路带有使能控制端,并且通过调节少量的外部元件可以改变电路的振荡频率,适用作各类中／低频数字集成电路中的时钟产生电路。分析了改进结构环形振荡器的工作原理,给出了Hspice软件环境下电路仿真方法。电路流片封装后的实际测试结果表明,用该结构的环形振荡器作为时钟产生电路,工作稳定,满足了系统工作要求。     

A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning

A 7-GHz CMOS voltage controlled ring oscillator that employs multiloop technique for frequency boosting is presented in this paper. The circuit permits lower tuning gain through the use of coarse/fine frequency control. The lower tuning gain also translates into a lower sensitivity to the voltage at the control lines. Fabricated in a standard 0.13- $mu$m CMOS process, the proposed voltage-controlled ring oscillator exhibits a low phase noise of $-$103.4 dBc/Hz at 1 MHz offset from the center frequency of 7.64 GHz, while consuming a current of 40 mA excluding the buffer.      

45ps的超高速全耗尽CMOS/SOI环振

亚微米全耗尽 SOI( FDSOI) CMOS器件和电路经过工艺投片 ,取得良好的结果 ,其中工作电压为 5V时 ,0 .8μm全耗尽 CMOS/ SOI1 0 1级环振的单级延迟仅为 45ps;随着硅层厚度的减薄和沟道长度的缩小 ,电路速度得以提高 ,0 .8μm全耗尽 CMOS/ SOI环振比 0 .8μm部分耗尽 CMOS/ SOI环振快 30 % ,比 1 μm全耗尽 CMOS/ SOI环振速度提高 1 5% .     

RF Oscillator Based on a Passive RC Bandpass Filter

A passive RC bandpass filter (BPF) based voltage-controlled-oscillator (VCO) operating at 2.5 GHz is presented. In GHz frequency range, a preferred type of an oscillator is either an LC oscillator or a ring oscillator. An LC oscillator exhibits an excellent phase noise performance while its fabrication cost is expensive due to the inductors. On the other hand, a ring oscillator can be built with standard CMOS devices resulting in a cheap fabrication cost. However, it has a poor phase noise and jitter performance and is sensitive to power supply noise. This paper proposes a RC BPF-based oscillator. Its property is closer to a LC oscillator rather than a ring oscillator and, as a result, improves the jitter performance due to power supply noise. Also, it can be fabricated in a standard CMOS process since there is no inductor. To prove the proposed concept, a RC BPF-based oscillator was designed and fabricated in a standard 0.13-$mu{hbox {m}}$ CMOS technology. An operating frequency of 2.5 GHz and phase noise of $-$ 95.4 dBc/Hz at 1$~$MHz offset was measured. Power consumption was 2.86 mW from a 1.3$~$ V supply voltage.      

A wide-locking range 6-phase divide-by-3 injection-locked frequency divider

A 6-phase divide-by-3 CMOS injection locked frequency dividers (ILFDs) have been proposed and implemented in a 0.35 μm CMOS process. The ILFD circuits are realised with a 3-stage double cross-coupled CMOS ring oscillator. The self-oscillating voltage controlled oscillator (VCO) is injection-locked by 3th-harmonic input to obtain the division factor of 3. Measurement results show that as the supply voltage varies from 1.2 to 3.5 V, the free-running frequency is from 0.136 to 0.7 GHz. At the incident power of ?5 dBm, the locking range in the divide-by-3 mode is from the incident frequency 0.38–2.31 GHz.     

Circuit Techniques for CMOS Divide-By-Four Frequency Divider

This letter describes circuit techniques for obtaining divide-by-four (divide4) frequency dividers (FDs) from CMOS ring-oscillator based injection locked frequency dividers (ILFDs). The circuit is made of a two-stage differential CMOS ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. At the supply voltage of 1.8V and at the incident power of 0dBm, for a dual-band ILFD, the divide4 ILFD can provide a locking range of 6.3% from 5.39 to 6.12GHz at low band and 5.9% from 8.84 to 9.38GHz at high band when the dc bias of MOS switches V_inj changes from 0.7 to 1.1V     

A Wide Band Injection Locked Frequency Divider With Variable Inductor Load

This letter proposes a new wide band CMOS injection locked frequency divider (ILFD). The circuit is made of a two-stage differential CMOS ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. A tuning circuit composed of inductors in series with a metal oxide semiconductor field effect transistor is used to extend the locking range. The divide-by-two ILFD can provide wide locking range and the measured results show that at the supply voltage of 1.8 V, the free-running frequency of the ILFD is operating from 0.92 to 3.6 GHz while the Vtune is tuned from 0 to 1.8 V. At the incident power of 0 dBm, this ILFD has a wide locking range from 1.15 to 7.4 GHz     

Frequency equation for the submicron CMOS ring oscillator using the first order characterization

By utilizing the first order behavior of the device,an equation for the frequency of operation of the submicron CMOS ring oscillator is presented.A 5-stage ring oscillator is utilized as the initial design,with different Beta ratios,for the computation of the operating frequency.Later on,the circuit simulation is performed from 5-stage till 23-stage,with the range of oscillating frequency being 3.0817 and 0.6705 GHz respectively.It is noted that the output frequency is inversely proportional to the square of the device length,and when the value of Beta ratio is used as 2.3,a difference of 3.64％ is observed on an average,in between the computed and the simulated values of frequency.As an outcome,the derived equation can be utilized,with the inclusion of an empirical constant in general,for arriving at the ring oscillator circuit's output frequency.     

一种伪差分两级环形振荡器的设计

设计了一种伪差分两级环形振荡器,可为锁相环提供8 GHz四相位正交时钟。通过分析耦合两级环形振荡线性模型,对四级环形振荡结构进行优化,提出了伪差分两级环形振荡结构。基于单级缓冲器的开环分析,可对振荡器的输出频率进行精准估算,并判断振荡情况。采用65 nm CMOS工艺进行设计与仿真。结果表明,在1.2 V电压下,振荡器的功耗为6.9 mW,1 MHz频率处的相位噪声为－82.104 5 dB,满足高速SerDes接口的设计要求。     

Co-integration of GaAs MESFET and Si CMOS circuits

Co-integration of GaAs MESFET and Si CMOS circuits is demonstrated using GaAs-on-Si epitaxial growth on prefabricated Si wafers. This is thought to be the first report of circuit-level integration of the two types of devices in a coplanar structure. A 2-μm gate Si CMOS ring oscillator has shown a minimum delay of 570 ps/gate, whereas on the same wafer a 1-μm gate GaAs MESFET buffered-FET-logic (BFL) ring oscillator has a minimum delay of only 70 ps/gate. A composite ring oscillator consisting of Si CMOS invertors and GaAs MESFET invertors connected in a ring has been successfully fabricated     

A Temperature Compensated CMOS Ring Oscillator for Wireless Sensing Applications

This paper presents a CMOS voltage controlled ring oscillator (VCO) with temperature compensation circuit suitable for low-cost and low-power MEMS gas sensor. This compensated ring oscillator is dedicated to Chopper Stabilized CMOS Amplifier (CHS-A). To operate at low frequency, a control voltage generated by a CMOS bandgap reference (BGR) is described and the measurement results of the fabricated chips are presented. The output voltage of the reference is set by resistive subdivision. In order to achieve small area and low power consumption, n-well resistors are used. This design features a reference voltage of 1 V. The chip is fabricated in AMS 0.35 μm CMOS process with an area of 0.032 mm². Operating at 1.25 V, the output frequency is within 200?±?l0 kHz over the temperature range of ?25 °C to 80 °C with power consumption of 810 μW.     

两种集成高频CMOS多谐压控振荡器

提出了两种压控振荡器,一种为差分形式,另一种为压控环结构．采用CSMC公司0.6μm标准CMOS工艺进行模拟,后仿真的结果显示,压控环结构的最高频率达到2GHz,在5V电源下的功耗为7.5mW．对压控振荡器的实现方法进行了分析比较,总结了高性能压控振荡器应具备的条件,并讨论了特定工艺下压控振荡器的极限频率．     

A CMOS Direct Injection-Locked Frequency Divider With High Division Ratios

A CMOS injection-locked frequency divider (ILFD) with high division ratios and high frequency operation is presented. It consists of a ring oscillator and injection capacitors. An input signal is directly injected through the capacitors into the feedback nodes of the ring oscillator. The proposed ILFD is fabricated in a $0.18~mu{rm m}$ CMOS process and has a chip core size of $68~mu{rm m}times 70~mu{rm m}$. It shows multiple division ratios of 3, 6, and 9. The operation frequency is from 2.2 to 30.95 GHz. At the maximum operation frequency, the ILFD has a locking range of 260 MHz with an input power of less than 0.25 dBm, a division ratio of 9, and a power consumption of 12.5 mW. The locking range increases up to 3.2 GHz as the division ratio and the operation frequency decrease.      

A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS

This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.     

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radiocommunications

CMOS inductorless voltage controlled oscillator (VCO) design is discussed with the emphasis on low-noise, low-power, gigahertz-range circuits suitable for portable wireless equipment. The paper considers three VCO structures-one simple ring oscillator and two differential circuits. The design methodology followed optimization for high-speed and low-power consumption. The proposed linearized MOSFET model allows the accurate prediction of the operating frequency while the phase noise evaluation technique makes it possible to determine, through simulation, the relative phase-noise performance of different oscillator architectures. The measurement results of three VCO's implemented in 1.2-μm CMOS technology confirm with the simulation predictions. The prototype VCO's exhibits 926-MHz operation with -83 dBc/Hz phase noise (@ 100 kHz carrier offset) and 5 mW (5 V) power consumption