Layered Approx-Regular LDPC: Code Construction and Encoder/Decoder Design

Layered approximately regular (LAR) low-density parity-check (LDPC) codes are proposed, with which one single pair of encoder and decoder support various code lengths and code rates. The parity check matrices of LAR-LDPC codes have a "layer-block-cell" structure with some additional constraints. An encoder architecture is then designed for LAR-LDPC codes, by making two improvements to the Richardson-Urbanke approach: the forward substitution operation is entirely removed and the dense-matrix-vector multiplication is handled using feedback shift-registers. A partially parallel decoder architecture is also designed for LAR-LDPC codes, where a layered modified min-sum decoding algorithm is used to trade off among complexity, speed, and performance. More importantly, the interconnection network, which is inevitable for partially parallel decoders, has much lower hardware complexity compared with that for general LDPC codes. Both the encoder and decoder architectures are highly flexible in code length and code rate.     

GB20600标准的LDPC码的改进

尽管LDPC码已经被GB20600标准采纳作为信道编码,与其它LDPC码相比,在同样码长和码率的情况下,GB20600 LDPC码误码率性能并非最佳;GB20600标准的LDPC码的码长达7493,存在编码复杂性问题,但是GB20600 LDPC码未采用基于校验矩阵的快速算法,这给GB20600 LDPC编解码器的硬件实现带来较大的困难。本文在现有GB20600 LDPC码的设计框架下,对GB20600中LDPC码的校验矩阵进行了修改,在此基础上提出一种有效的LDPC码的快速迭代算法,使编解码器的硬件易于实现。改进后的LDPC码的编码算法具有较低的实现复杂度。仿真结果表明,改进后的LDPC码的误包率性能优于现GB20600中LDPC码的误包率性能。      

Quasi‐regular rate‐compatible LDPC codes with a novel diagonal‐tailed encoding on noisy channels

It is well known that conventional rate‐compatible (RC) codes, such as Raptor codes, only perform well at long code lengths. However, we propose a class of RC codes with short code lengths in this paper. Particularly, we develop a computational approach to design online‐generated RC low‐density parity‐check (LDPC) codes available on noisy channels. We first propose a diagonal‐tailed encoding to generate Quasi‐regular low‐density generator matrix codes. Then, an optimal encoding profile for RC codes is achieved with a linear interpolation approach that is based on the fixed‐rate quasi‐regular LDPC codes. Finally, we evaluate the rateless and fixed‐rate performances of the proposed RC codes by extensive simulation results on various code rates with different modulations. Copyright © 2013 John Wiley & Sons, Ltd.     

Euclidean Geometry LDPC-VBLAST System Design and Performance Evaluation

Among popular multi-transmit and multi-receive antennas techniques, the VBLAST (Vertical Bell Laboratories Layered Space-Time) architecture has been shown to be a good solution for wireless communications applications that require the transmission of data at high rates. Recently, the application of efficient error correction coding schemes such as low density parity-check (LDPC) codes to systems with multi-transmit and multi-receive antennas has shown to significantly improve bit error rate performance. Although irregular LDPC codes with non-structure are quite popular due to the ease of constructing the parity check matrices and their very good error rate performance, the complexity of the encoder is high. Simple implementation of both encoder and decoder can be an asset in wireless communications applications. In this paper, we study the application of Euclidean geometry LDPC codes to the VBLAST system. We assess system performance using different code parameters and different numbers of antennas via Monte-Carlo simulation and show that the combination of Euclidean geometry LDPC codes and VBLAST can significantly improve bit error rate performance. We also show that interleaving data is necessary to improve performance of LDPC codes when a higher number of antennas is, used in order to mitigate the effect of error propagation. The simplicity of the implementation of both encoder and decoder makes Euclidean geometry LDPC codes with VBLAST system attractive and suitable for practical applications.     

光通信系统中LDPC码的构造及其编译码算法分析

针对低密度奇偶校验（LDPC）码的相关理论和LDPC码自身特性以及光通信系统具有低噪声、高信噪比的传输特点进行分析后,提出了光通信系统中LDPC码型的构造方法,这为光通信系统中LDPC码型的构造和仿真分析奠定了基础。并对光通信系统中LDPC码的编译码算法进行了深入分析与研究,得到一些有利于降低其编译码算法复杂度的重要结论,这有助于降低其编译码器的设计与实现复杂度。     

面向5G标准的低延时LDPC编码器设计

针对 5G 标准中对低延时和编码灵活性的要求, 本文提出了一种高并行度的低密度奇偶校验(Low-Density Parity-Check, LDPC)码编码算法并设计了相应的硬件结构。 编码算法对校验位的计算流程进行了改进, 通过将对应 5G 标准中校验矩阵单对角和双对角结构的不同编码步骤并行化提高了运算速度。 在硬件结构上一方面设计了多路并行的运算结构通过同时求解多个编码步骤降低了处理时延, 另一方面灵活的结构设计使其可以有效地支持5G不同场景下对码长和码率的要求, 并通过分组计算校验位实现了对递增冗余的HARQ (IR-HARQ)方案的支持。仿真结果表明,在 200 MHZ 的系统时钟频率下, 本设计的信息吞吐量可达 35Gbps。      

Joint (3,k)-regular LDPC code and decoder/encoder design

Recently, low-density parity-check (LDPC) codes have attracted a lot of attention in the coding theory community. However, their real-world applications are still problematic mainly due to the lack of effective decoder/encoder hardware design approaches. In this paper, we present a joint (3,k)-regular LDPC code and decoder/encoder design technique to construct a class of (3,k)-regular LDPC codes that not only have very good error-correcting capability but also exactly fit to high-speed partly parallel decoder and low-complexity encoder implementations. We also develop two techniques to further modify this joint design scheme to achieve more flexible tradeoffs between decoder hardware complexity and decoding speed.     

LDPC码编码器实现方法

LDPC码是一种系统复杂度低的线性纠错码,其实用化受到了业界的广泛关注。文章概述了LDPC码的基本编码原理,从硬件实现角度概括了LDPC码编码器五种硬件实现方法并对其进行分析,最后指出LDPC码编码器的硬件实现及其发展趋势。     

Rate-compatible puncturing of low-density parity-check codes

In this correspondence, we consider puncturing of low-density parity-check (LDPC) codes for additive white Gaussian noise (AWGN) channels. We show that good puncturing patterns exist and that the puncturing can be performed in a rate-compatible fashion. Furthermore, rate-compatible puncturing results in a small loss of performance with respect to threshold, namely, the punctured code is good (in terms of threshold) across a range of rates when compared with the optimal codes for each rate. This allows one to implement a single "mother" encoder and decoder that is good across a wide range of rates.     

A Versatile Variable Rate LDPC Codec Architecture

This paper presents a system architecture for low-density parity-check (LDPC) codes that allows dynamic switching of LDPC codes within the encoder and decoder without hardware modification of these modules. Thus, rate compatibility is facilitated without the performance degradation inherent in a puncture-based system. This versatility also allows the LDPC system to be used in a variety of applications since the encoder and decoder can be used with codes that span a wide range of lengths and rates.     

多元速率兼容LDPC码的自适应编码调制系统研究

本文设计了一种基于有限域GF(q)上的多元速率兼容LDPC (RC-LDPC) 码结合高阶调制的自适应编码调制(Adaptive Coded Modulation, ACM) 系统。并提出了多元RC-LDPC码在独立和相关衰落信道下的增量冗余型自适应编码调制方案。本方案中多元LDPC码码率从1/3到5/6灵活变化,以较低的系统复杂度,有效提高了系统的频带利用率。仿真结果表明:随着系统吞吐率提高,多元ACM系统相对于二元ACM系统具有越来越明显的编码增益,最高可达约9 dB。      

符合CCSDS标准的动态可重构LDPC编码器的FPGA设计

CCSDS标准的LDPC生成矩阵具有分块循环特征,并且各种码率的生成矩阵的校验部分都可以分解为8×x的形式,提出利用CCSDS标准的LDPC的特点设计动态可重构LDPC编码器。首先提出了LDPC编码器码速率重构的4种模型,然后分析了功能重构的关键技术模块,最后对码速率重构进行了仿真,并对仿真结果和综合结果进行了分析,结果与理论分析一致。     

Performance Analysis of Parallel Concatenation of LDPC Coded SISO-GFDM System for Distinctive Pulse Shaping Filters using USRP 2901 Device and its Application to WiMAX

The increasing demand for high data rates requires channel error control codes for the upcoming fifth generation. This article presents an investigation of the parallel concatenation of low-density parity-check codes (PC-LDPC) in the fifth generation proposed waveform candidate called generalized frequency division multiplexing (GFDM). PC-LDPC codes are obtained by dividing the long and high complexity single LDPC codes into small two lower complexity codes, and these designed codes are applied to the 5G-GFDM waveform. Since the GFDM signal transmits data in both the time and frequency domain, these PC-LDPC codes can deal with two-dimensional errors. This channel coded GFDM system is integrated into Universal software radio peripheral (USRP) device for real-time implementation. The Attainment of the proposed transceiver is verified by computation of BER under distinctive channel coding techniques like convolutional, Golay, Bose-Chaudhuri-Hochquenghem (BCH), extended length single LDPC code. The different pulse shaping filters such as Raised Cosine (RC), Root Raised Cosine (RRC), Gaussian, and Xia 4th order filter are applied to the GFDM under the Gaussian noise and Rayleigh fading channel to compute Out of band (OOB) power. The PC-LDPC coded GFDM outperforms LDPC by 6.5 dB in the RRC filter for roll-off factor rate 0.5 under the Rayleigh fading channel. PC-LDPC code outperforms LDPC code with a coding gain of 2 dB was observed in IEEE 802.16 Transceiver.

     

An innovative low-density parity-check code design with near-Shannon-limit performance and simple implementation

A novel parity-check matrix design for low-density parity-check (LDPC) codes is described. By eliminating the routing problem associated with LDPC codes, the design results in a small implementation area, and the codes have outstanding error-rate performance close to the Shannon limit for a wide range of code rates, from 1/4 to 9/10, and for various modulation schemes such as binary phase-shift keying (PSK), quaternary PSK, 8-PSK, 16-amplitude PSK (APSK), and 32-APSK. As a result, LDPC codes designed with this method have been standardized for next-generation digital video broadcasting.     

Flexible construction of irregular partitioned permutation LDPC codes with low, error floors

Irregular partitioned permutation (IPP) low-density parity-check (LDPC) codes have been recently introduced to facilitate hardware implementation of belief propagation (BP) decoders. In this letter, we present a new method to construct IPP LDPC codes with great flexibility in the selection of code parameters. Meanwhile, small stopping sets are avoided in the code construction, thus good error floor performance can be achieved.     

高效低功耗低并行度LDPC编码方法

低密度奇偶校验码(LDPC)是最接近香农极限的纠错码之一,具有优良的性能且被国际通信标准组织广泛采纳为信道编码。CCSDS推荐使用LDPC码作为近地空间和深空探测的信道编码方案。该文提出高效,低功耗,低并行度的LDPC编码方法。该方法通过采用插0和改变循环矩阵的结构实现了对CCSDS标准中推荐的校验矩阵子矩阵大小为奇数的LDPC码的低并行度编码。通过分析编码过程,提出了只对输入信息中的1有效信息位进行编码的方案,减少了编码中移位寄存器的移位次数,大幅度地降低了编码器功耗。文中采用FPGA实现了(8176, 7154)78LDPC码的编码器,结果显示在硬件开销略有增加的情况下,编码功耗大幅度下降,编码速率接近低并行度编码方案。     

Reversible Low-Density Parity-Check Codes

Low-density parity-check (LDPC) codes may be decoded using a circuit implementation of the sum-product algorithm which maps the factor graph of the code. By reusing the decoder for encoding, both tasks can be performed using the same circuit, thus reducing area and verification requirements. Motivated by this, iterative encoding techniques based upon the graphical representation of the code are proposed. Code design constraints which ensure encoder convergence are presented, and then used to design iteratively encodable codes, while also preventing 4-cycle creation. We show how the Jacobi method for iterative matrix inversion can be applied to finite field matrices, viewed as message passing, and employed as the core of an iterative encoder. We present an algebraic construction of 4-cycle free iteratively encodable codes using circulant matrices. Analysis of these codes identifies a weakness in their structure, due to a repetitive pattern in the factor graph. The graph supports pseudo-codewords of low pseudo-weight. In order to remove the repetitive pattern in the graph, we propose a recursive technique for generating iteratively encodable codes. The new codes offer flexibility in the choice of code length and rate, and performance that compares well to randomly generated, quasi-cyclic and extended Euclidean-geometry codes.     

基于DVB-S2的通用LDPC编码器的FPGA设计

针对DVB-S2标准中的LDPC码编码器,提出了一种基于FPGA的通用LDPC编码器设计,该编码器具有多码率通用的特点,并且利用IPCORE构造出多个ROM和RAM,实现了在同一信息位输入时所有与之关联校验位的并行处理,提高了编码速度.经试验测试表明,编码器能够稳定工作,处理速率约为63.371 Mbit/s,满足DVB-S2中不同码率下LDPC编码器的需求.     

LDPC码全并行译码器的设计与实现

本论文用可编程逻辑器件(FPGA)实现了一种低密度奇偶校验码(LDPC)的编译码算法.采用基于Q矩阵LDPC码构造方法,设计了具有线性复杂度的编码器. 基于软判决译码规则,采用全并行译码结构实现了码率为1/2、码长为40比特的准规则LDPC码译码器,并且通过了仿真测试.该译码器复杂度与码长成线性关系,与Turbo码相比更易于硬件实现,并能达到更高的传输速率.     

Codes for iterative decoding from partial geometries

This paper develops codes suitable for iterative decoding using the sum-product algorithm. By considering a large class of combinatorial structures, known as partial geometries, we are able to define classes of low-density parity-check (LDPC) codes, which include several previously known families of codes as special cases. The existing range of algebraic LDPC codes is limited, so the new families of codes obtained by generalizing to partial geometries significantly increase the range of choice of available code lengths and rates. We derive bounds on minimum distance, rank, and girth for all the codes from partial geometries, and present constructions and performance results for the classes of partial geometries which have not previously been proposed for use with iterative decoding. We show that these new codes can achieve improved error-correction performance over randomly constructed LDPC codes and, in some cases, achieve this with a significant decrease in decoding complexity.