Hot-carrier degradation behavior of N- and P-channel MOSFET's underdynamic operation conditions

An in-depth study of the dynamic hot-carrier degradation behavior of N- and P-channel MOS transistors was performed based on the change of charge pumping and I-V characteristics. It is shown that for transistors with channel lengths ranging from 2 to 0.5 μm and frequencies up to 100 MHz the degradation under dynamic stress can completely be described as a quasi-static degradation, provided all static degradation effects are taken into account in the appropriate way. This means that the influence of post-stress effects and charge buildup or charge detrapping have to be considered     

A study of hot carrier degradation in NMOSEET's by gate capacitanceand charge pumping current

Hot carrier degradation in n-channel MOSFET's is studied using gate capacitance and charge pumping current for three gate stress voltages: V_g~V_b, V_d/2, V_d. The application of these two sensitive techniques reveals new information on the types of trap charges and the modes of degradation. At low V_g stress near threshold voltage, the fixed charge is attributed to holes. For high V_g stress, the fixed charge is predominantly electrons. Data for mid V_g stress suggest little net fixed charge trapping. Interface traps are observed for all stress conditions and are demonstrated from differential gate capacitance spectra to exhibit both donor and acceptor trap behavior. Mid V_g stress is shown to result in the highest density of interface traps. These traps can be annealed to a large extent for temperatures up to 300°C. A post-stress generation of interface traps is observed at low V_g stress, in agreement with recent observation. Further, a linear relation is found to exist between the change in overlap gate capacitance and the increase in peak charge pumping current, and suggests spatial uniformity in the degradation of the interface     

A novel single-device DC method for extraction of the effectivemobility and source-drain resistances of fresh and hot-carrier degradeddrain-engineered MOSFET's

A new DC technique, the drain current-conductance method (DCCM), has been developed to extract the gate bias dependent effective channel mobility (μ_eff), and source and drain series resistance (R _s and R_d) of drain-engineered MOSFET's. The extraction of μ_eff, R_e, and R_d by DCCM is based on the DC measurements of drain current and conductance of a single device. The negligible difference between the measured and modeled (using the extracted parameters) linear drain current showed that the DCCM is accurate and effective for devices with different graded junction structures and channel lengths. Asymmetry between R_s and R_d for LDD p-MOSFET's was found to be more significant than for LATID n-MOSFET's. This asymmetry has invalidated many methods which utilized the assumptions of R_d=R_s for the extraction of device parameters. The DCCM was further applied to devices with nonuniform hot-carrier degradation. The μ_eff, R_s, and R_d of LATID n-MOSFET's degraded under different hot-carrier stress conditions were extracted. The increase in R_d is found to dominate the initial phase of hot-carrier degradation while the decrease in μ_eff intensifies as the stress duration increases. The extracted parameters have provided physical insight into the asymmetries of graded junctions and degradation mechanisms of hot-carrier stressed MOSFET's, The DCCM is especially useful for the extraction of SPICE parameters that are usable in circuit and reliability simulation     

Performance and hot-carrier reliability of 100 nm channel lengthjet vapor deposited Si3N4 MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si₃N₄ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO₂ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si₃N₄ barrier (2.1 eV) is lower than the Si-SiO₂ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO₂ MOSFETs     

A comparison of hot-carrier degradation in tungsten polycide gateand poly gate p-MOSFETs

A study is made of hot-carrier immunity of tungsten polycide and of non-polycide, n⁺ poly gate, buried-channel p-MOSFETs, under conditions of maximum gate current injection. Increased hot-carrier degradation is observed for WSi_x p-MOSFETs under low drain voltage stress, where trap filling by injected electrons is the dominant degradation process. Stress-induced damage evaluated by gate-to-drain capacitance C_gd^s measurement shows increased susceptibility to electron trapping in the WSi_x device. F-induced oxide bulk defects introduced during polycidation may be responsible for the increased trapping observed. In addition, a significant decrease in electron detrapping rate is observed, which suggests a deeper energy distribution of F-related traps. The greater susceptibility to electron trapping, coupled with a decrease in electron detrapping rate, result in the reduction in DC hot-carrier lifetime over four orders of magnitude (based on ΔV_t=50 mV criterion) under normal operating voltages. As hot-carrier effects in p-MOSFETs continue to be a concern for effective channel lengths less than 0.5 μm, the reduced hot-carrier lifetime of WSi_x p-MOSFETs suggests that WF₆-based silicidation may not be appropriate for deep submicrometer CMOS devices     

The characterization of hot carrier damage in p-channel transistors

Damage in surface channel p-MOS transistors arising from hot-carrier stress is examined using a recently proposed lifetime extraction method. It is shown that the p-MOS behavior with respect to hot-carrier stress runs counter to that of n-MOS transistors in many respects and has to be considered separately. Not only are the well-known post-stress gains in drive current obtained for p-MOS transistors, but also the measurement of the I-V characteristics with the stress damage at the source and drain ends shows effects opposite to those of n-MOS devices. This is attributed to coulombic screening by the channel charge. Stressing transistors in inverter-like and pass-transistor-like modes are also discussed, and it is found that p-MOS transistors are much more sensitive to pass-transistor-like damage than n-channel devices, due to increased channel length shortening in the pass transistor mode. It is shown that whereas at long gate lengths (>0.5 μm) the degradation is limited to drain current changes, at shorter channel lengths (<0.5 μm), significant threshold voltage shifts arise     

Dependence of hot-carrier immunity on channel length and channelwidth in MOSFETs with N2O-grown gate oxides

The authors report on the channel length (0.5-5 μm) and width (0.6-10 μm) dependence of hot-carrier immunity in n-MOSFETs with N ₂O-grown gate oxides (~85 Å). While channel hot-carrier-induced degradation has a strong dependence on channel geometry in control devices, the degradation and its channel geometric dependences are greatly suppressed in devices with N₂O-gate oxides. Under Fowler-Nordheim injection stress, the control device shows an enhanced degradation with decreasing channel length and increasing channel width, whereas N₂O device exhibits a less dependence on channel geometry     

CMOS current steering logic for low-voltage mixed-signal integratedcircuits

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of ΔV_logic≈V_dd , a CSL gate swings only ΔV_logic≈V_T+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100× smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 μm high-V_T n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 μm process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V_T and low-V_T CSL ALU's were operational at V _dd≈=0.70 V and V_dd≈0.40 V, respectively     

A 0.4-μm gate-length AlGaAs/GaAs P-channel HIGFET with 127-mS/mmtransconductance at 77 K

WN-gate, p-channel AlGaAs-GaAs heterostructure insulated-gate field-effect transistors (HIGFETs) fabricated on a metalorganic vapor-phase epitaxy (MOVPE) wafer are discussed. A self-aligned Mg ion implantation (80 keV, 6×10¹³ cm^-2) annealed at 850°C in an arsine atmosphere and the control of the SiO₂ sidewall dimensions allow the fabrication of p-channel HIGFETs with a gate length smaller than 0.5 μm with low subthreshold current. P-channel HIGFETs with 0.4-μm gate lengths exhibit extrinsic transconductances as high as 127 mS/mm at 77 K and 54 mS/mm at 300 K     

0.3-μm gate length p-channel AlGaAs/InGaAs heterostructure fieldeffect transistors with high cut-off frequency

P-channel Heterostructure Field Effect Transistors (HFETs) with a 0.3-μm gate were fabricated by Mg ion implantation. The maximum transconductance was 68 mS/mm and there was no serious drain or gate leakage current, regardless of this short gate length. The gate turn on voltage (@I_gs=-1 μA/μm) was -2.1 V and its absolute value was large enough for use in complementary HFETs. S-parameters measurements showed a very high cut-off frequency of over 10 GHz. Results indicated the superiority of less-diffusive Mg ion implantation for forming p⁺-layer in p-channel HFETs     

1.5 nm direct-tunneling gate oxide Si MOSFET's

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 μm, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA/μm and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 μm at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used     

Sub-60-nm quasi-planar FinFETs fabricated using a simplifiedprocess

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 μA/μm (or 1 mA/μm, depending on the definition of the width of the double-gate device) for V_g-V _t=V_d=1 V. The electrical gate oxide thickness in these devices is 21 Å, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness     

Degradation due to electrical stress of poly-Si thin filmtransistors with various LDD lengths

The degradation phenomena of polycrystalline silicon (poly-Si) thin film transistors (TFT's) with various lightly-doped drain (LDD) length have been investigated. It is observed that the threshold voltage shift due to electrical stress varies with LDD length. The threshold voltage shift after 4 hours electrical stress of V_g=V_d =30 V in conventional, 0.5 μm, and 2 μm LDD poly-Si TFT's are about 2.7 V, 5.2 V, and 0.8 V, respectively     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds     

Gate length scaling in high performance InGaP/InGaAs/GaAs pHEMTs

The performance of InGaP-based pHEMTs as a function of gate length has been examined experimentally. The direct-current and microwave performance of pHEMTs with gate lengths ranging from 1.0-0.2 μm has been evaluated. Extrinsic transconductances from 341 mS/mm for 1.0 μm gate lengths to 456 mS/mm for 0.5 μm gate lengths were obtained. High-speed device operation has been verified, with f_t of 93 GHz and f_max of 130 GHz for 0.2 μm gate lengths. The dependence of DC and small-signal device parameters on gate length has been examined, and scaling effects in InGaP-based pHEMT's are examined and compared to those for AlGaAs/InGaAs/GaAs pHEMTs. High-field transport in InGaP/InGaAs heterostructures is found to be similar to that of AlGaAs/InGaAs heterostructures. The lower ϵ_r of InGaP relative to AlGaAs is shown to be responsible for the early onset of short-channel effects in InGaP-based devices     

Fabrication and characterization of a depletion-mode ZnS0.07Se0.93 MESFET

We report the fabrication and characterization of a depletion-mode n-channel ZnS_0.07Se_0.93 metal-semiconductor field effect transistor (MESFET). A ZnSSe FET could be a key element in opto-electronic integration consisting of light emitters, light receivers and MESFET pre-amplifiers. Mesa isolation, recess etching and self-alignment techniques were adopted to optimize the MESFET performance. Source and drain (S/D) ohmic contacts and gate Schottky contact were formed by Cr/In/Cr and Au deposition, respectively. Depletion mode FET's with varying gate width-to-length ratio of W/L=200 μm/20 μm, 200 μm/4 μm and 200 μm/2 μm were fabricated. A 2 μm FET was characterized as follows: the turn-on voltage, V_on≈1.75 V, the pinch-off voltage, V_p≈-13 V, the unit transconductance, g_m≈8.73 mS/mm, and the breakdown voltage with zero gate-source bias, BV≈28 V     

A thorough investigation of the degradation induced by hot-carrierinjection in deep submicron N- and P-channel partially and fullydepleted unibond and SIMOX MOSFETs

A thorough investigation of hot-carrier effects in deep submicron N- and P-channel SOI MOSFET's is reported in this paper. First, a comparison of device aging among three types of SOI devices fabricated by various technologies is shown. The carrier type, the quality of oxides, and the device structure are key parameters for the degradation mechanisms in these devices. On the other hand, the worst-case aging (V _d=V_t,V_d/2 or V_d) also depends on these device distinctions. For fully depleted SOI MOSFETs, the variation of the main electrical parameters is determined with and without the influence of defects in the buried oxide. The device lifetime of NMOS/SOI in the worst-case condition is carefully predicted using accurate methods that take into account the degradation saturation and the region of defect creation (Si/SiO₂ interface and/or oxide volume). Finally, an investigation of the aging/recovery mechanisms is carried out in P-channel SOI MOSFETs under an alternating stress     

Deep-submicrometer CMOS technology with reoxidized or annealednitrided-oxide gate dielectrics prepared by rapid thermalprocessing

Deep submicrometer CMOSFETs with re-annealed nitride-oxide gate dielectrics have been demonstrated to satisfy 3.3-V operation, unlike conventional oxide FETs. The 1/4-μm re-annealed nitrided-oxide CMOS devices achieve (1) an improved saturation transconductance g _m of ~250 μS/μm for n-FETs together with acceptably small degradation in p-FET g_m resulting in a CMOS gate delay time of 55 ps/stage comparable or superior to the device/circuit performance of oxide FETs, and (2) device lifetimes improved by ~100 times to exceed 10 years with respect to both ON- and OFF-state hot-carrier reliability for n-FETs as well as gate-dielectric integrity together with unchanged p-FET hot-carrier reliability, all at 3.3-V operation. To achieve these CMOS performance/reliability improvements, both a light nitridation and subsequent re-annealing in O ₂ (reoxidation) or in N₂ (inert-annealing) are found to be crucial     

Channel-length-independent hot-carrier degradation in analog p-MOSoperation

The hot-carrier degradation of p-MOSFETs in analog operation is investigated. In accordance with analog operation requirements, the damage is characterized by the drain conductance and the data are taken from devices with channel lengths between 1 and 10 μm. In the important saturation range, a strong channel-length-independent degradation of the drain conductance is found. This result is explained by a simple analytic model. Other parameters such as the drain current or the transconductance show the usual channel length dependence. These results show that an increase in channel length does not generally solve problems related with hot-carrier degradation. Furthermore, the common digital hot-carrier constraints are shown to be insufficient to cover analog applications     

Hot-carrier degradation of p-MOSFET's under analog operation

The hot-carrier degradation of p-MOSFET's is investigated from the viewpoint of analog operation. We apply sensitive measurement methods to determine drain current, drain conductance, and transconductance in the saturation regime besides the commonly investigated parameters in the linear regime of operation. Those investigations are performed for different gate lengths in order to allow comparisons between the shortest channels used for digital and the long channels usually used for analog operation, it is found that the drain conductance important in many analog applications, does not show a channel length dependence for gate lengths above 1.5 times the minimum gate length. The stress time dependencies are determined predominantly finding logarithmic behaviors. These findings are explained by a model which highlights the importance of the lengths of the regions of damage and carrier velocity saturation. Moreover, the dependencies of the different characterization parameters on stress time, channel length and voltages of operation are evaluated. Finally, methods are given for extrapolation of degradation of analog parameters to operating conditions for reliability assurance