Through-thickness characterization of copper electrodeposit

Through-thickness crystallographic texture, defect structure, and tensile embrittlement of 35 μm thick electrodeposit are characterized by successive thinning. An initially random grain structure, inherited from the substrate, evolves into a strong <220> fiber texture. The random to oriented grain transformation begins at the inception of thickening and is complete after about 15 μm deposit thickness, where about 0.9 volume fraction of grains become oriented near <220>. Further thickening of the deposit sharpens the texture, reducing the scatter around the <220> ideal orientation. A duplex coarse/fine particle (coherent domain) structure is obtained. Coarse particles along <220> are less defective and have smaller lattice strains; fine particles along <200>, presumably associated with the random grains, are defect-saturated with finely spaced twins, high dislocation density and enhanced lattice strains. With increasing distance from the shiny surface (of initial film formation), especially following the initial 10 μm deposit thickness, (a) along <220>: particle size and twin spacing increase whereas dislocation density and root mean square (rms) strains decrease, (b) along <200>: particle size increases gradually, dislocation density and rms strains increase sharply and the already fine twin spacing remains unchanged, and (c) the effective particle size ratio D_eff<220>:D_eff<200> exceeds 1.4, suggesting a twinning-induced z-direction particle shape anisotropy. A substantial decrease in tensile elongation is observed at 180°C. The embrittlement increases with the deposit thickness, attributed to the development of low density regions in the morphological boundaries. High elongation and embrittlement directional anisotropies are observed near the shiny surface, perhaps due to preferred nucleation on the substrate asperities.     

Effects of microstructure on interconnect and via reliability: Multimodal failure statistics

The reliability of interconnects and contacts depends on their microstructure. However, a large change in the average grain size does not necessarily positively affect reliability. When grain sizes and feature sizes are comparable, interconnect and via reliability depends much more strongly on the nature of the grain size distribution and the probability of occurrence of specific microstructural features, than on the average grain size. Also, when grain sizes and feature sizes are comparable, different microstructure-specific failure mechanisms can occur, and multimodal failure statistics are often observed. In this case, if failure data are incorrectly fit to a single failure-time distribution, the resulting reliability assessment may be pessimistic or optimistic, but is in any case, incorrect. In this regime, accurate reliability assessment requires a detailed knowledge of the microstructure of the interconnects, and a characterization of the failure of the weakest microstructural features present in the population to be assessed.     

Local textures and grain boundaries in voided copper interconnects

We have characterized grain boundary structures and local textures in stress voided copper lines. Grain boundary misorientations as well as the tilt and twist character of boundaries were measured using electron backscatter diffraction in the scanning electron microscope in conjunction with focused ion beam images. We have summarized data for a number of boundaries immediately adjacent to voids and made comparisons to boundaries from regions that remained intact. These data were acquired from the same lines, and so represent measurements from material with identical histories. Significant local variations in microstructure were observed. Local <111> textures of grains near voids were of lower strength than those away from voids. Grain boundaries intersecting voids were of higher angle character and had significant twist components. These results suggest that local regions associated with more favorable kinetics are more susceptible to void formation and growth.     

Texture and microstructure of thin copper films

Microstructure is an important factor influencing the reliability of thin film interconnects. The microstructure of copper films is of particular interest because of its use in numerous electronic applications. Pole figure x-ray diffraction and transmission electron microcopy were conducted on copper films deposited by several techniques: sputtering, partially ionized beam deposition, chemical vapor deposition, evaporation, and electroplating. Quantitative texture data are determined from fiber texture plots. A typical copper film consists of three texture components: (111), (200), and random. (220) and (511) texture components are possible under some deposition conditions. Compared to aluminum films, the fraction of the random texture component and the distribution of the (hkl) components in copper films are relatively large. Bimodal grain size distributions are observed in some films.     

Analysis of thermal stresses in copper interconnect/low-k dielectric structures

Numerical simulations of thermal stresses in copper (Cu) interconnect and low-k dielectric systems are carried out. The three-dimensional (3-D) finite-element analysis assumes a two-level metal structure connected by a via. Mechanical deformation is generated by thermal expansion mismatches during cooling and cyclic temperature changes. The thin barrier/etch stop layers, as well as oxide or polymer-based low-k dielectric materials, are all taken into account in the model. The stress and deformation fields are examined in detail; salient features having direct implications in device reliability are illustrated with representative contour plots. It is found that the use of low-k material in place of traditional oxide dielectric significantly reduces the triaxial tensile stresses in Cu but enhances plastic deformation, especially in the via region. The compliant low-k material causes the thin barrier layers to bear very high stresses. Deformation in the Cu line and via structure is more affected by the thermal expansion property of the dielectric, but the stresses in the barrier layers are more influenced by the elastic modulus of the dielectric.     

Grain nucleation and texture analysis of electroless copper deposition on a palladium seed layer

Electroless copper grains were deposited on a Pd seed layer under varying bath conditions. The seed layer was determined to have a (111) texture using grazing incident x-ray (GIX) diffraction. Multiple nucleation sites in the grain boundaries were imaged using a scanning tunneling microscope. Continual copper growth produced row-like structures. The texture of the electrolessly deposited copper (ED-Cu) grains were determined to be (111). No radial grain orientation for the Pd seed layer or the ED-Cu thin film was detected using GIX diffraction. Atomic force microscope images indicated continual Cu nucleation throughout the deposition process. PdH was formed as a by-product of the electroless deposition process, and detected by x-ray diffraction.     

Deformation and interfacial sliding in back-end interconnect structures in microelectronic devices

Deformation of interconnect structures at the back-end of microelectronic devices during processing or service can have a pronounced effect on component reliability. Here, we use atomic force microscopy (AFM) to study plastic deformation and interfacial sliding of Cu interconnects on Si. The behavior of both standalone Cu lines and lines embedded in a low-K dielectric (LKD) was studied. Following thermal cycling, changes were observed in the in-plane (IP) Cu line dimensions, as well as the out-of-plane (OOP) step height between Cu and the dielectric in single-layer structures. These were attributed to differential deformation of the Cu/Si and Cu/dielectric material pairs caused by thermal expansion mismatch, accommodated by interfacial creep. These results are discussed in light of previous work on the mechanism of interfacial creep. A simple shear-lag-based model, which may be used to estimate the extent of interfacial sliding, is proposed. Some experimental results on the distortion of Cu lines caused by package-level stresses following thermal cycling are also presented.     

Texture investigation of copper interconnects with a different line width

To understand the effect of line width on textural and microstructural evolution of Cu damascene interconnect, three Cu interconnects samples with different line widths are investigated. According to x-ray diffraction (XRD) results, the (111) texture is developed in all investigated lines. Scattered {111}〈112〉 and {111}〈110〉 texture components are present in 0.18-μm-width interconnect lines, and the {111}〈110〉 texture was developed in 2-μm-width interconnect lines. The directional changes of the (111) plane orientation with increased line width were investigated by XRD. In addition, microstructure and grain-boundary character distribution (GBCD) of Cu interconnect were measured using electron backscattered diffraction (EBSD) techniques. This measurement demonstrated that a bamboo-like microstructure is developed in the narrow line, and a polygranular structure is developed in the wider line. The fraction of ∑3 boundaries is increased as the line width increases but is decreased in the blanket film. A new interpretation of textural evolution in damascene interconnect lines after annealing is suggested, based on the state of stress and growth mechanisms of Cu deposits.     

Electromigration-induced failures in interconnects with bimodal grain size distributions

Interconnects containing bimodal grain size distributions are known to have lower me-dian times to electromigration-induced failure (MTTF). However, the deviation in the time to failure (DTTF) in such lines has not been well characterized. We find that Al-2%Cu-0.3%Cr interconnects with bimodally distributed grain sizes have MTTF’s which are more than an order of magnitude lower than lines with monomodally distributed small grain sizes. However, the DTTF’s for both types of lines are similar, and in fact slightly lower for lines with bimodal structures. An activation energy of 0.85 eV was obtained both for lines with monomodal large grain structures and bimodal grain struc-tures, suggesting that grain boundary diffusion is the controlling mechanism in both cases. A model based simply on microstructural characteristics,e.g. the distribution of the number of grain boundaries, can explain the lower MTTF’s and DTTF’s for lines with bimodal structures. The implications of bimodal grain size distributions on the reliability of large numbers of lines are discussed. Also, a new, convenient graphical tool for illustrating the failure rate of interconnects with lognormally distributed failure times is presented.     

Textural and microstructural transformation of Cu damascene interconnects after annealing

Influence of annealing on the textural and microstructural transformation of Cu interconnects having various line widths is investigated. Two types of annealing steps have been considered here: room temperature over 6 months and 200°C for 10 min. The texture was determined by x-ray diffraction (XRD) of various cross-sectional profiles after electropolishing, and the surface, microstructure, and grain boundary character distribution (GBCD) of Cu interconnects were characterized using electron backscattered diffraction (EBSD) techniques. In order to analyze a relationship between the stress distribution and textural evolution in the samples, microstresses were calculated with decreasing line widths at 200°C using finite element modeling (FEM). In this investigation, it was found that the inhomogeneity of stress distribution in Cu interconnects is an important factor, which is necessary for understanding textural transformation after annealing. A new interpretation of textural evolution in damascene interconnects lines after annealing is suggested, based on the state of stress and the growth mechanisms of Cu electrodeposits.     

Study of ultrathin vanadium nitride as diffusion barrier for copper interconnect

Ultrathin Vanadium nitride (VN) thin film with thickness around 10 nm was studied as diffusion barrier between copper and SiO₂ or Si substrate. The VN film was prepared by reactive ion beam sputtering. X-ray diffraction, Auger electron spectroscopy, scanning electron microscopy and current-voltage (I-V) technique were applied to characterize the diffusion barrier properties for VN in Cu/VN/Si and Cu/VN/SiO₂ structures. The as-deposited VN film was amorphous and could be thermal stable up to 800 °C annealing. Multiple results show that the ultrathin VN film has good diffusion barrier properties for copper.     

Variable-shaped e-beam lithography enabling process development for future copper damascene technology

To realize fast and efficient integrated circuits the interconnect system gains an increasing importance. In particular, this is the case for logic and processor circuits with up to 12 metallization layers. In order to optimize this technology and the according processes it is desirable to generate flexible test structures in small lot production. In opposition to standard optical lithography using masks, Electron Beam Direct Write (EBDW) lithography can rapidly deliver special test structures at low cost. Furthermore, critical dimensions of future technology nodes which are not yet manufacturable by standard optical lithography tools can be produced. In this paper we demonstrate the potential of the 50 kV variable shaped EBDW cluster for patterning of future back-end-of-line (BEOL) structures on full 200 mm wafers. The patterned wafers have been used to develop next generation copper damascene interconnect processes for critical dimensions down to 50 nm.     

Effect of copper seed aging on electroplating-induced defects in copper interconnects

Voids in copper thin films, observed after electroplating, have been linked to seed aging that occurs when a wafer is exposed, over time, to clean-room ambient. Oxidation of the copper seed surface prevents wetting during subsequent copper electroplating, leading to voids. Several surface treatments were employed to counteract the seed aging effect, including reduction of the copper oxide film by hydrogen, reverse plating of the copper surface, and rinsing the wafer surface with electrolyte. Each treatment was applied to wafers increasingly aged from 2 to 14 days, just prior to electroplating. Results showed a significant decrease in postelectroplating defects with all three treatments. The reduction of copper oxide by hydrogen exhibited the most marked results. An increase in surface wetting is shown by a decrease in contact angle measurements and an increase in film reflectivity for treated versus untreated copper wafers. This study shows that, although the copper surface exhibits strong aging effects over a short period of time, using proper surface treatments can eliminate such effects and voids.     

Enhanced stress-migration reliability for ULSI interconnect: An insight into the perils of screening Al depositions based on grain size

The recent trend toward increasing packing density and the demand for improved reliability have dramatically challenged ultra large scale integrated circuit technologists to develop more robust fabrication processes. Finer feature sizes and the addition of layers of interconnect, combined with large mechanical stresses, have greatly exacerbated the insidious problem of stress-induced voiding—open circuits can appear in Al lines immediately after fabrication or after years of shelf storage. Finite element analysis shows that one of the prime candidates for controlling the root cause of the failure mechanism, stress-assisted grain-boundary diffusion, is carefully engineered Al grain size. This paper examines various parameters related to grain size that directly result in mechanically weak populations of interconnect elements. We highlight some critical factors that give rise to unique implementation issues, including the complex statistical nature of the susceptible sites and the evolution of the microstructure during device fabrication. The resulting experimental reliability enhancement can be startling—a new deposition process accounted for a 350% increase in lifetime in sub-micron wide lines.     

Physical investigation of the impact of electrolessly deposited self-aligned caps on insulation of copper interconnects

With the miniaturization of ULSI circuits and the associated increase of current density up to several MA/cm², copper interconnects are facing electromigration issues at the top interface with the dielectric capping layer SiC(N). A promising solution is to insert selectively on top of copper lines a CoWP metallic self-aligned encapsulation layer, deposited using a wet electroless process. We study the impact of this process on electrical line insulation as a function of cap thickness at the 65 nm technology node and we investigate the physical origin of leakage currents. Below a critical thickness, only a slight leakage current increase of less than one decade is observed, remaining within the specification for self-aligned capping layer processes. Above this critical thickness, large leakage currents are generated due to the combined effect of lateral growth and the presence of parasitic redeposited nodules. We show that a simple phenomenological model allows to reproduce the experimental data, to assess quantitatively the contribution of parasitic defects, and to predict that the self-aligned barrier technology should be extendible up to the 32 nm node, provided that a thin cap layer of less than 8 nm is used.     

Effects of barrier layer and processing conditions on thin film Cu microstructure

The crystallographic texture and grain size of sputtered Cu films were characterized as a function of deposition temperature, barrier layer material, and vacuum conditions. For Cu deposited in a HV chamber, (111) Cu texture was found to weaken with increasing deposition temperatures on W, amorphous C and Ta barrier layers, each deposited at 30°C. Conversely, under identical Cu deposition conditions, texture was found to strengthen with increasing deposition temperature on Ta deposited at 100°C. Median Cu grain size varied parabolically with deposition temperature on all barrier layers and was slightly higher on the 100°C Ta at a given Cu deposition temperature, relative to the other underlayers. For depositions in an UHV chamber, Cu texture was found to strengthen with increasing Cu deposition temperature, independent of Ta deposition temperature. Median Cu grain size, however, was still higher on 100°C Ta than on 30°C Ta. The observed differences between the two different chambers suggest that the trend of weak texture at elevated deposition temperatures may be related to contamination. Characterization of the Ta underlayers revealed that the strengthened texture of Cu films deposited on 100°C Ta is likely related to textural inheritance.     

铜互连线静水应力的有限元模拟

本文根据工业上使用的铜大马士革互连线尺寸建立了三维有限元模型,模拟计算了铜大马士革互连线中对应力诱导形成空洞很关键的静水应力分布,对比分析了不同低k介质、阻挡层材料和互连线深宽比对静水应力的影响。研究结果表明,静水应力受k介质、阻挡层材料和互连线深宽比影响很大,静水应力在铜大马士革互连线中分布不均匀且最大应力出现在互连线表面。     

Effects of Copper Doping on Microstructural Evolution in Eutectic SnBi Solder Stripes under Annealing and Current Stressing

Effects of Cu doping on the microstructural evolution in the eutectic SnBi solder stripes under annealing and current stressing were investigated. Coarsening of the Bi grains was observed in the eutectic SnBi solder upon annealing at 85°C. Doping of 1 wt.% Cu could significantly reduce the grain coarsening rate from 2.8 to 0.5 μm³/h. In addition to grain coarsening, mass accumulation of Bi at the anode and solder depletion at the cathode of the eutectic SnBi solder stripe stressed by a current of 1.3 × 10⁴ A/cm² at 85°C were also observed. Doping of 1 wt.% Cu could also reduce the grain coarsening of the solder under current stressing; however, it resulted in an enhancement of the electromigration effect. Accumulation of Bi at the anode and the solder depletion at the cathode became more severe in the Cu-doped solder stripe.     

Finite element simulation of hydrostatic stress in copper interconnects

This work focuses on numerical modeling of hydrostatic stress,which is critical to the formation of stress-induced voiding(SIV) in copper damascene interconnects.Using three-dimensional finite element analysis, the distribution of hydrostatic stress is examined in copper interconnects and models are based on the samples, which are fabricated in industry.In addition,hydrostatic stress is studied through the influences of different low-k dielectrics,barrier layers and line widths of copper lines,and the results indicate that hydrostatic stress is strongly dependent on these factors.Hydrostatic stress is highly non-uniform throughout the copper structure and the highest tensile hydrostatic stress exists on the top interface of all the copper lines.