An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line

A wide-range delay-locked loop (DLL) with infinite phase shift and digital-controlled duty cycle is presented. By changing the polarity of the input clock of the voltage-controlled sawtooth delay, this proposed DLL achieves infinite phase shift by only a single loop. The proposed DLL has been fabricated in a 0.18$ mu$m CMOS process and the core area is $hbox{0.45}times {hbox{0.3 mm}}^{2}$. The measurement results show the proposed DLL operates from 50 to 500 MHz. The duty cycle of the output clock can be adjusted from 30% to 60% in the step of 5%. At 500 MHz, the measured rms jitter and peak-to-peak jitter is 1.43 and 11.1 ps, respectively. Its power consumption is 6 mW for a supply of 1.5 V.      

A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop

A 20-MHz to 3-GHz wide-range multiphase delay-locked loop (DLL) has been realized in 90-nm CMOS technology. The proposed delay cell extends the operation frequency range. A scaling circuit is adopted to lower the large delay gain when the frequency of the input clock is low. The core area of this DLL is 0.005 $hbox{mm}^{2}$. The measured power consumption values are 0.4 and 3.6 mW for input clocks of 20 MHz and 3 GHz, respectively. The measured peak-to-peak and root-mean-square jitters are 2.3 and 16 ps at 3 GHz, respectively.      

A 120-MHz–1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-$muhbox m$CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07$hbox mm^2$and has a peak-to-peak jitter of$pm $6.6 ps at 1.3 GHz.     

A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles.     

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

A DLL featuring jitter reduction techniques for a noisy environment is described. It controls a loop response mode by monitoring the magnitude of input jitter caused by supply noise. This technique varies the probability of phase error tracking. It reduces the output jitter of the DLL due to a low effective variance of input phase error and a narrow effective loop bandwidth. The DLL is implemented in a 0.13 $muhbox{m}$ CMOS process. Under noisy environments, the output clock of 1 GHz has 4.58 ps RMS and 29 ps peak-to-peak jitter.      

A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock

A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-${rm mu}hbox{m}$ CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 $hbox{mm}^{2}$ and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.      

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

In this paper, a delay-locked loop (DLL)-based clock generator is presented. Although a DLL-based clock generator requires a clean reference signal, it has several inherent advantages over conventional phase-locked-loop-based clock generators, i.e., no jitter accumulation, fast locking, stable loop operation, and easy integration of the loop filter. We propose a phase detector with a reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problems of the conventional DLL-based system. Fabricated in a 0.35-/spl mu/m CMOS process, our DLL-based clock generator occupies 0.07 mm/sup 2/ of area and consumes 42.9 mW of power. It operates in the frequency range of 120 MHz-1.1 GHz and has a measured cycle-to-cycle jitter of /spl plusmn/7.28 ps at 1 GHz. The die area, peak-to-peak, and r.m.s. jitter are the smallest compared to those of reported high-frequency clock multipliers.     

A Single-Stage Direct Interpolation Multiphase Clock Generator with Phase Error Averaging

Multiphase clock generators are conventionally implemented with a feedback loop. This paper presents a non-feedback approach to generate multiphase clocks. A simple architecture of direct phase interpolation is proposed, in which the edges of two phase-adjacent signals are used to control the discharge (or charge) of two capacitors respectively, producing time-overlapped slopes. A resistor chain connected to the two capacitors is used to interpolate a number of new slopes in between. The generated phase resolution depends on the number and ratios of resistors thus is not limited by an inverter delay. Based on this architecture, a multiphase clock generator is developed. In addition, a phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a 0.35 m, 3.3 V CMOS process. The measured performance shows it can produce 8 evenly spaced clock signals in one input clock period and work in an input clock range from 300 MHz to 600 MHz. The measured maximum jitter performance is rms 6.8 ps and peak-to-peak 47 ps, respectively.     

A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode

This paper presents a low-power digital DLL-based clock generator. Once the DLL is locked, it operates in open-loop mode to reduce deterministic clock jitter and the power dissipation caused by DLL dithering. To keep track of any potential phase error introduced by environmental variations, a compensation mechanism is employed. In addition, a robust DLL-based frequency multiplication technique is proposed. The DLL-based clock generator is designed and fabricated in a 90 nm CMOS process in two different versions. Utilizing the proposed technique, the output jitter caused by DLL dithering is reduced significantly. Furthermore, the measured total power savings in the open-loop mode in comparison with the conventional closed-loop operation is about 14%.      

A 0.7-2-GHz self-calibrated multiphase delay-locked loop

A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks in the proposed DLL can be self-calibrated. When the calibration procedure is finished, the digital calibration circuit can be turned off automatically to save power dissipations and reduce noise generations. A start controlled circuit is proposed to enlarge the operating frequency range of the DLL. Both the start-controlled circuit and the calibration circuit require an external reset signal to ensure the correctness of the calibration after temperature,operating frequency, and power supply voltage are settled. This DLL with the digital calibration circuit has been fabricated in a 0.18-/spl mu/m CMOS process. The measured results show the DLL exhibits a lock range of 0.7-2 GHz while the peak-to-peak jitter and rms jitter is 18.9ps and 2.5 ps at 2 GHz, respectively. When the calibration procedure is completed and the DLL operates at 1 GHz, the maximum mismatch-induced timing error among multiphase clocks is reduced from 20.4 ps (7.34 degree) to 3.5 ps (1.26 degree).     

An all-analog multiphase delay-locked loop using a replica delayline for wide-range operation and low-jitter performance

This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. The proposed DLL keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. The DLL incorporates dynamic phase detectors and triply controlled delay cells with cell-level duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip has been fabricated using a 0.35-μm CMOS process. The peak-to peak jitter is less than 30 ps over the operating frequency range of 62.5-250 MHz, At 250 MHz, its jitter supply sensitivity is 0.11 ps/mV. It occupies smaller area (0.2 mm²) and dissipates less power (42 mW) than other wide-range DLL's [2]-[7]     

A $Delta{-}Sigma$ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology

A triangular-modulated spread-spectrum clock generator using a$Delta{-}Sigma$-modulated fractional-$N$ phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to implement the modulated fractional counter with increased $Delta{-}Sigma$ operation speed. In addition, the phase mismatching error in the phase-interpolated PLL with multiphase clocks can be randomized, and finer frequency resolution is achievable. With a frequency modulation of 33 kHz, the measured peak power reduction is more than 11.4 dB under a deviation of $pm$0.37%. Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. After spread-spectrum operation, the measured up-spread and down-spread jitter can achieve 52.59 and 56.79 ps, respectively. The chip occupies $950times850 {rm mu}{rm m}^{2}$ in 0.18-${rm mu}{rm m}$ CMOS process and consumes 36 mW.      

A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- μm CMOS Technology

A 37-38.5-GHz clock generator is presented in this paper. An eight-phase LC voltage-controlled oscillator (VCO) is presented to generate the multiphase outputs. The high-pass characteristic CL ladder topology sustains the high-frequency signals. The split-load divider is presented to extend the input frequency range. The proposed PD improves the static phase error and enhances the gain. To verify the function of each block and modify the operation frequency, two additional testing components-an eight-phase VCO and a split-load frequency divider-are fabricated using 0.13-mum CMOS technology. The measured quadrature-phase outputs of VCO and input sensitivity of the divider are presented. This clock generator has been fabricated with 0.13-mum CMOS technology. The measured rms clock jitter is 0.24 ps at 38 GHz while consuming 51.6 mW without buffers from a 1.2-V supply. The measured phase noise is -97.55 dBc/Hz at 1-MHz offset frequency     

A 2.5-GHz four-phase clock generator with scalable no-feedback-looparchitecture

An accurate yet simple multiphase clock generator has been developed by using a delay compensation technique based on phase interpolation that supplies a multiphase clock signal without increasing local circuit area. This generator is applied to the 2.5-GHz four-phase clock distribution of a 5-Gb/s×8-channel receiver fabricated with 0.13-μm CMOS technology. The four-phase generator in the receiver consumes 30 mW and occupies only 0.009 mm². It requires only 1.5 clock cycles to produce accurate phase differences and can operate from 1.5 to 2.8 GHz, with a range of phase error within ±5     

A DLL-Based Variable-Phase Clock Buffer

A variable-phase clock buffer that uses a delay-locked loop (DLL) is presented. The variable-phase clock is achieved by switching the multiphase outputs of the divider in the DLL. The output phase is adjustable in a step of where pi/n is the ratio of two voltage-controlled delay lines in the proposed circuit. The prototype has been fabricated in a 0.18- CMOS process to realize the output phases of 0deg, 90deg, 180deg, and 270deg. The corresponding measured phase error is 3.24deg, 3.46deg, 3.89deg, and 1.94deg, respectively. The measured root-mean-squared jitter is 1.81 ps. The clock buffer consumes 67 mW including I/O circuits from a single 1.8-V supply at 600 MHz.     

A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver

A 2.5-GHz built-in jitter measurement (BIJM) system is adopted to measure the clock jitter on a transmitter and receiver. The proposed Vernier caliper and autofocus approaches reduce the area cost of delay cells by 48.78% relative to pure Vernier delay line structure with a wide measurement range. The counter circuit occupies an area of 19 $mu$ m $times$ 61 $mu$ m in the traditional stepping scan approach. The proposed equivalent-signal sampling technique removes the input jitter transfer path from the sampling clock. The power supply rejection design is incorporated into the delay cell and the judge circuit. The layout implementation, calibration, and test time of the proposed BIJM system are all improved. The core circuit occupies an area of only 0.5 mm $times$ 0.15 mm with the 90-nm CMOS process. The Gaussian and uniform distributions jitter is verified at a 5-ps timing resolution and a 2.5-GHz input clock frequency .      

A 0.004-mm2 Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-mum and in a 0.13-mum CMOS technologies. They consist of a full-digital CMOS circuit design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that enables clock-on-demand circuit structures. The implemented low power clock generator tile in a 0.13-mum CMOS technology occupies only 0.004 mm ² and operates at variable input frequencies ranging from 625 MHz to 1.2 GHz within a plusmn 2% phase error having one-cycle lock time.     

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS

This paper presents a clock generator circuit for a high-speed analog-to-digital converter (ADC). A time-interleaved ADC requires accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at a speed of 166 MS/s, which corresponds to an equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 μm SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies a 0.6 mm² silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted using 1 ps precision.     

A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in0.25-μm SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 × 16 b input data buffer are integrated in a 0.25-μm SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 × 16 b input data buffer accommodates ±2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking modes. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI_P-P over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB     

A 1.5 GHz All-Digital Spread-Spectrum Clock Generator

An all-digital spread-spectrum clock generator (SSCG) has been fabricated in a 0.18 $mu{hbox {m}}$ CMOS process. The analysis and design of this all-digital SSCG is presented. A mixed-signal phase and frequency detector is adopted to reduce the jitter, eliminate a digital adder, and also reduce latency. A Vernier time-to-digital converter (TDC) with time amplifiers is realized to enhance the timing resolution of the TDC and to track the frequency modulation in the SSCG. A digitally controlled oscillator with a resolution enhancement circuit is also presented. The measured electromagnetic interference reduction is 10.48 dB. The measured peak-to-peak jitter and rms jitter are 28.4 ps and 4$~$ps, respectively, at 1.5 GHz.