p-Channel MOS transistor in indium antimonide

A p-channel MOS transistor in InSb single crystal, operating at 77 K, is described. The source and drain are defined by etching a mesa structure in a cadmium diffused p layer into a tellurium-doped InSb substrate. The gate is formed by evaporation of chromium gold on top of a layer of SiO2, deposited at 215°C. The MOS transistor is characterized by a threshold voltage of -3 V and an effective hole mobility of 330 cm². V^-1.s^-1.     

Profiling interface traps in MOS transistors by the DCcurrent-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 10¹¹ traps/cm² generated by channel hot electron stress     

A model for the breakdown characteristics of p-channel MOS transistor protection devices

Gate controlled diodes, MOS transistors with grounded gate, source and substrate and gate controlled pnn + structures are compared when used as a protective input device on p-channel MOS integrated circuits. For this purpose two pulse techniques are developed which allow an accurate determination of the dynamic resistance by minimizing the walk-out of the breakdown voltage during the measurement. While the breakdown voltage does not differ much for the different types of devices, the dynamic resistance however is found to be considerably lower for the MOS transistor than for both other devices. For these low values the series resistance of the drain and source diffusion is shown to constitute already an important contribution. The lower dynamic resistance of MOST's can be ascribed to parasitic bipolar transistor operation during breakdown. The identification of this mechanism leads to a simple model for the MOS transistor in breakdown which has been experimentally verified and confirmed. Guidelines for the definition of the source diffusion for an optimal protective functioning can be obtained from this model.     

FCAT—A low-voltage high-speed alterable n-channel nonvolatile memory device

The structure and principles of a new nonvolatile charge storage device are described. The Floating Si-gate Channel Corner Avalanche Transition (FCAT) memory device is an n-channel MOS transistor with a floating gate. The p⁺regions are placed outside the channel area by aligning them with the floating gate and are adjacent to the diffused n⁺source and/or drain regions. This device can operate in the write/erase modes under low-voltage (12 V) and high-speed (< 1 ms) conditions using only a pair of positive pulses. This is achieved with a novel avalanche transition at the channel corner through a relatively thin (4-6 nm thick) oxide under the open-drain condition.     

Electrical characteristics of a DSA MOS transistor with a fine structure

Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor. The drain current IDof the symmetrical DSA MOS transistor is, respectively, 1.13 (in the nonsaturation region) and 1.33 (in the saturation region) times larger than that of the conventional short-channel NMOS transistor at the effective gate voltage of 3.0 V. The improvement of the short-channel effect, the current voltage characteristics, and the power-delay product are obtained by the scaling of the DSA MOS transistor.     

Effects of deliberate copper contamination from the platingsolution on the electrical characteristics of MOSFETs

N-channel and p-channel metal-oxide-semiconductor (MOS) transistors of various (W/L) ratios down to 0.24-μm channel length have been used to investigate the effects of deliberate backside copper (Cu) contamination on the MOS field-effect transistor (MOSFET) electrical parameters. The backside of the wafer was flooded with copper sulphate (CuSO₄) solution and air-dried. High-temperature annealing was carried out to drive Cu into silicon. It was discovered that the backside Cu contamination did not result in any undesirable effects on the MOS device performance. The MOS device parameters such as threshold voltage V_TO, transconductance G_m, drain saturation current I_DSAT, off-current I_off, and junction leakage current for n⁺/p and p+/n diodes displayed no significant degradation, even after 5 h of annealing at 400°C in nitrogen ambient. Secondary ion mass spectroscopy data shows that Cu diffused into silicon only over a short distance, leading to little or no degradation of MOSFETs and junction diodes     

Analysis of high-frequency thermal noise of enhancement mode MOS field-effect transistors

The high-frequency thermal noise in the drain and the gate of an enhancement mode MOS field-effect transistor was analyzed by using the transmission line model of the channel. The analysis gave the mean squared noise current generators of the drain and the gate and their correlation. The correlation coefficient of the drain and the gate noise was zero for zero drain voltage and was 0.395j at saturation. The noise figure of the MOS field-effect transistor was calculated from the result of the analysis. The high-frequency noise characteristics of an MOS field-effect transistor were similar to those of a junction gate field-effect transistor.     

Modification of most I-V characteristics by self-heating

A MOS transistor, when passing drain current, dissipates power in the channel region. This results in a temperature rise within the channel area, which can modify the I-V behaviour of the transistor. In this paper, we have calculated the channel temperature as a result of power dissipated by the device, by solving the heat diffusion equation. The modified I-V behaviour of the MOS transistor due to this channel heating has been predicted and matches experimentally observed phenomena. In particular, the negative dynamic resistance observed in the saturation region of MOS transistors operating at elevated power densities has been explained.     

Fundamental limitations in microelectronics—I. MOS technology

The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain ‘corner’ breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10⁷–10⁸ MOS transistors per cm².     

Optimum design of n+-n-double-diffused drain MOSFET to reduce hot-carrier emission

Channel electric field reduction using an n⁺-n^-double-diffused drain MOS transistor to suppress hot-carrier emission is investigated. The double-diffused structure consists of a deep low-concentration P region and a shallow high-concentration As region. The channel electric field strongly depends on such process and device parameters as the length of the n^-diffusion region, drain junction depth, gate oxide thickness, gate length, applied voltage, and P implant energy. The optimum condition for a double-diffused structure is determined based on those parameter dependences of the channel electric field. The results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region. The hot-carrier immunity of MOSFET and test circuits are improved by two orders of magnitude and one order of magnitude, respectively, under the optimum conditions.     

Short-channel MOSFET VT-VDScharacteristics model based on a point charge and its mirror images

Short-channel MOS transistordV_{T}/dV_{DS}characteristics are expressed by an analytic function of fundamental device parameters. The expression is derived from a simple model of short-channel MOS transistors in threshold condition, which is based on a point charge and its mirror images. With this expression,dV_{T}/dV_{DS}is found to be proportional to1/L^{2}-1/L^{4}, whereLis channel length. Following factors are also found, wherein the source and drain junction depth effect is only logarithmic ondV_{T}/dV_{DS}characteristics,dV_{T}/dV_{SUB}anddV_{T}/dV_{DS}are closely related in short-channel MOS transistors, and short-channel effects are expected to be smaller in MOS transistors on SOS than on bulk silicon, due to a large number of Si/sapphire interface states. This model is simple, and it can be applied to short-channel MOS transistor designing and circuit simulations.     

Evidence of optical generation of minority carriers from saturated MOS transistors

Minority carrier injection into the substrate by a MOS transistor operating in saturation presents a reliability problem in dynamic memory circuits such as RAM's and CCD's. The effect has been studied by measuring the substrate and drain currents of stressed transistors as a function of gate and drain voltages, firstly by the accumulation of minority carriers in a charge coupled device, and secondly by the direct detection of light from the drain region of a transistor. These results suggest that light emission associated with multiplication in the drain region is more important than the secondary impact ionization mechanism in the generation of minority carriers.     

Velocity saturation effect on short-channel MOS transistor capacitance

To analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree quite well. Several causes of short-channel effects are explained by the simulations. Velocity saturation effects are found to play a key role in the gradual increase in Cgd. Also holes in the accumulation region and the two-dimensional effect or the influence of the back-gate field from the drain are important in explaining the short-channel effect of MOS transistor capacitance.     

A novel trench-isolated buried N+FAMOS Transistor suitable for high-density EPROM's

This paper describes an innovative use of trench isolation to achieve high programmability and improved isolation in a high-density electrically programmable read-only memory (EPROM) cell. This cell, with a 13.5-µm²area at 1.5-µm design rules, was fabricated by using a novel cross-point structure with buried N+ (BN+) bit lines as source and drain of the floating-gate avalanche injection MOS (FAMOS) transistor. Programming efficiency and bit-line isolation were enhanced by a novel positioning of the trench isolation between bit-lines and between the double-polysilicon FAMOS transistors. Trench isolation should permit scaling of the bit-line spacing to below 1 µm.     

An electrical mechanism for holding time degradation in dynamic MOS RAM's

Holding time degradation due to electrically generated excess minority carriers has been observed in a 16-kbit dynamic MOS RAM. The failure mode is described by two-step impact ionization in a drain depletion region of a transistor and a subsequent diffusion process. Other experiments by a dynamic MOS RAM cell test device, a charge-coupled device, and a He-Ne laser for carder excitation, consistently verify the mechanism which leads to degradation of stored information. In addition, the actual failure map is successfully reproduced by an optical experiment, and also in a computer simulation. Effects of electrical excess minority-carrier generation are discussed from a reliability point of view, particularly for dynamic MOS LSI's.     

The insulated gate tunnel junction triode

The gate modulated voltage breakdown of the drain diode in the MOS transistor is considered and shown to be direct electric field control of a reverse biased surfacep+-njunction. A structure designed to isolate this effect has been suggested by Atalla and experimentally evaluated by Nathanson, et al., and by the authors. The mechanism of operation discussed involves the application of an external electric field normal to the surface of the highly doped side of the junction to produce direct field emission of carriers. The reverse biased low doped side of the junction then acts as a collector of the field-emitted carriers resulting in a net current flow across the junction. Using the Atalla structure, a model is presented and a quantitative theory is developed to explain and predict the device performance. It is found that the actual device may be represented as an MOS transistor in series with an "ideal" field-controlled tunnel junction, and that the performance of the actual device can never be better than that of the limiting MOS transistor. The theoretical characteristics of the ideal field-controlled tunnel junction are derived and found to agree closely with the experimental results. It is shown that, at the present time, the device is limited by the "ideal" tunnel junction region and not by the series MOS transistor.     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

Fabrication of Schottky barrier MOSFETs using self-assembly CoSi2 nanopatterning and spacer gate technologies

A self-assembly patterning method for generation of epitaxial CoSi₂ nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n⁺-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO₂ and 300 nm Si₃N₄. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi₂ layer and a subsequent out-diffusion process to form the n⁺-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated.     

The effect of fluorine on MOSFET channel length

The effect of fluorine on MOS device channel length has been evaluated. Fluorine has been introduced into the transistor by self-aligned ion implantation after the lightly doped drain (LDD) implant. The impact of fluorine in the LDD region, and its effect on the electrically determined channel length (L_eff), has been examined. Measurements taken from 0.6-μm LDD MOSFETs show a significant dependence of the L_eff on fluorine implant dose. The n⁺ resistor also shows more width reduction compared to unfluorinated samples. The decrease in channel length reduction by adding fluorine in the LDD region may yield way to relieve short-channel effects for the continuous scaling of CMOS devices into the deep-submicrometer region