Systolic architectures for finite-state vector quantization

We present a new systolic architecture for implementing Finite State Vector Quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is needed for speech compression. A linear array of processors is used for image compression; the number of processors needed is independent of the size of the image. We also present a simple architecture for converting line-scanned image data into the format required by this systolic architecture. Image data is processed at a rate of 1 pixel per clock cycle. An implementation at 31.5 MHz can quantize 1024×1024 pixel images at 30 frames/sec in real-time. We describe a VLSI implementation of these processors.     

Optical computing advances logically for image processing

A powerful application of optical computation, digital optical cellular image processing (DOCIP), is discussed. DOCIP uses digital optical computing techniques to perform cellular logic operations or extended array functions on images. Cellular logic is reviewed, and a binary image algebra (BlA) that serves as an analysis and synthesis tool for cellular image processing systems is described. Some DOCIP architectures that have been proposed or experimentally demonstrated are discussed and classified as image-algebra-type processors or symbolic-substitution-type processors. The optical and optoelectronic implementations of these architectures are also discussed     

A four-processor building block for SIMD processor arrays

A four-processor chip, for use in processor arrays for image computations, is described. The large degree of data parallelism available in image computations allows dense array implementations where all processors operate under the control of a single instruction stream. An instruction decoder shared by the four processors on the chip minimizes the pin count allocated for global control of the processors. The chip incorporates an interface to an external SRAM (static RAM) for memory expansion without glue chips. The full-custom 2-μm CMOS chip contains 56669 transistors and runs instructions at 10 MHz. Five hundred and twelve 16-b processors and 4 Mbyte of distributed external memory fit on two industry standard cards to yield 5-billion instructions per second peak throughout. As image I/O can overlap perfectly with pixel computation, an array containing 128 of these chips can provide more than 600 16-b operations per pixel on 512×512 images at 30 Hz     

Wavefront processing of radio-frequency wavefront data

A class of special-purpose processors is described. These processors are for use in holographic imaging systems that utilize electromagnetic waves with radio frequencies. The systems, which operate in very nearly real time, consist of arrays of receiving antennas with a receiver at each antenna. The received intensities control modulation in a second array of antennas that radiate waves generated by a coherent source at a frequency higher than the received waves. The processors are wavefront processors in two senses because they process received wavefronts and because the data flow resembles a wavefront. The processors are data driven so they require no clock, and they operate in parallel. Measurements with a prototype system are described, and a diffraction theory analysis of images is given. Extension to phase receivers and holograms are described, along with a discussion of visible image production in real time.     

Shunting neural network photodetector arrays in analog CMOS

This paper describes a custom analog CMOS photodetector array IC that exploits nonlinear lateral inhibition to achieve dynamic range compression, edge enhancement, and adaptation to mean input intensity. The neural net array architecture, characterized by nearest-neighbor connections and multiplicative cell interaction, is modeled after biological vision systems. The fabricated IC successfully implements a portion of the compact and powerful nonlinear signal processing performed in the outer layers of the vertebrate retina. Measured results are presented for an optical input intensity range of nearly six decades. A scanning architecture that allows for preferential directional sensitivity is also demonstrated. Measured data agree well with models created using a spreadsheet program     

基于USB的摄像机阵列的设计与实现

描述了一种新颖的图像采集系统--摄像机阵列,提出了一种可配置的摄像机阵列的结构.这个结构中的所有摄像机采用CMOS图像传感器采集图像,可以控制图像的尺寸和帧率.利用数字信号处理器(DSP)对图像进行处理和压缩,然后通过通用串行总线(USB)将来自所有摄像机的图像数据传送到PC进行存储和处理.     

浮点加法器的低功耗结构设计

浮点加法器是集成电路数据通道中重要的单元，它的性能和功耗极大地影响着处理器和数字信号处理器的性能。文章分析了浮点加法器的几种结构，重点介绍了实现低功耗的三数据通道结构。最后，还对浮点加法器结构的实用性进行了分析。     

Seasat Synthetic-Aperture Radar Data Reduction Using Parallel Programmable Array Processors

This paper presents a digital signal processing system that produces the SEASAT synthetic-aperture radar (SAR) imagery. The system consists of a SEL 32/77 host minicomputer and three AP-120B array processors. The partitioning of the SAR processing functions and the design of softwae modules is described. The rationale for selecting the parallel array processor architecture and the methodology for developing the parallel processing scheme on this system is described. This system attains a SEASAT SAR data reduction speed of 2.5 h per 25-m resolution 4-look and 100 km X 100 km image frame. A prelininary performance evaluation of this parallel processing system and potential future applications for remote sensing data reduction are described.     

A Programmable Imager for Very High Speed Cellular Signal Processing

In this paper a programmable imager with averaging will be described which is intended for averaging of different groups or sets of pixels formed by n × n kernels, n × m kernels or independent pixels of the array. This imager is a 64 × 64 array which uses passive pixels that can be randomly accessed. The read-outstage includes a sole charge amplifier with programmable gain, a sample-and-hold structure and an analog buffer. This read-out structure is different from other existing imagers with variable resolution since it uses a sole charge amplifier, whereas the normal structure is an operational amplifier per column plus a global operational amplifier. This structure will be described in detail indicating the advantages and disadvantages with respect to other imagers with averaging capabilities. This programmable resolution architecture can be more appropriate, and eventually, more efficient, when implementing very high speed Cellular Neural Network (CNN) processors in a CNN chipset—a mixed-signal hardware platform for CNN-based image processing. A significant processing time reduction can be obtained when decreasing the image resolution, and therefore the amount of information to be transferred to the CNN processor. This programmable resolution can also be used for fast image recognition and ulterior windowing at full resolution in a reduced area of the image, permitting a more accurate processing of the region of interest. In addition, full resolution images can still be obtained, as in commercial imagers which are usually included in CNN chipsets.     

Self-affine mapping system and its application to object contourextraction

A self-affine mapping system which has conventionally been used to produce fractal images is used to fit rough lines to contours. The self-affine map's parameters are detected by analyzing the blockwise self-similarity of a grayscale image using a simplified algorithm in fractal encoding. The phenomenon that edges attract mapping points in self-affine mapping is utilized in the proposed method. The boundary of the foreground region of an alpha mask is fitted by mapping iterations of the region. It is shown that the proposed method accurately produces not only smooth curves but also sharp corners, and has the ability to extract both distinct edges and blurred edges using the same parameter. It is also shown that even large gaps between the hand-drawn line and the contour can be fitted well by the recursive procedure of the proposed algorithm, in which the block size is progressively decreased. These features reduce the time required for drawing contours by hand.     

Extraction of left ventricular contours from left ventriculograms by means of a neural edge detector

We propose a method for extracting the left ventricular (LV) contours from left ventriculograms by means of a neural edge detector (NED) in order to extract the contours which accord with those traced by a cardiologist. The NED is a supervised edge detector based on a modified multilayer neural network, and is trained by use of a modified back-propagation algorithm. The NED can acquire the function of a desired edge detector through training with a set of input images and the desired edges obtained from the contours traced by a cardiologist. The proposed contour-extraction method consists of 1) detection of "subjective edges" by use of the NED; 2) extraction of rough contours by use of low-pass filtering and edge enhancement; and 3) a contour-tracing method based on the contour candidates synthesized from the edges detected by the NED and the rough contours. Through experiments, it was shown that the proposed method was able to extract the contours in agreement with those traced by an experienced cardiologist, i.e., we achieved an average contour error of 6.2% for left ventriculograms at end-diastole and an average difference between the ejection fractions obtained from the manually traced contours and those obtained from the computer-extracted contours of 4.1%.     

Image processing on a memory array architecture

In this paper we examine the usefulness of a simple memory array architecture to several image processing tasks. This architecture, called theAccess Constrained Memory Array Architecture (ACMAA) has a linear array of processors which concurrently access distinct rows or columns of an array of memory modules. We have developed several parallel image processing algorithms for this architecture. All the algorithms presented in this paper achieve a linear speed-up over the corresponding fast sequential algorithms. This was made possible by exploiting the efficient local as well as global communication capabilities of the ACMAA.     

Fast Implementation of 3-D Digital Filters Via Systolic Array Processors

In this paper a fast implementation architecture of three-dimensional (3-D) FIR or IIR digital filters via systolic VLSI array processors is described. The modular structure presented is comprised of similar processing elements in a linear cascade configuration with local interconnections. High speed throughput rates are attained due to high concurrency, which is achieved by exploiting both pipelining and parallelism. The considered 3-D FIR and IIR filters may be used for the processing of reconstructed 3-D images and in medical imaging applications.     

Circuit board inspection using a range camera

A high-speed, high-accuracy three-dimensional (3-D) range camera that possesses sufficient speed and accuracy to inspect circuit boards in real time is presented. The architecture of the system is briefly described, and the algorithms used to make quantitative presolder measurements, including the orientations and lengths of leads and the locations and shapes of holes, are examined in detail. Since the unit runs in real time and performs sophisticated image analysis functions, considerable emphasis in the algorithm development was placed on the ability to partition tasks between general-purpose computers and array processors     

Low-Power Parallel Video Compression Architecture for a Single-Chip Digital CMOS Camera

A low-power, large-scale parallel video compression architecture for a single-chip digital CMOS camera is discussed in this paper. This architecture is designed for highly computationally intensive image and video processing tasks necessary to support video compression. Two designs of this architecture, an MPEG2 encoder and a DV encoder, are presented. At an image resolution of 640 × 480 pixels (MPEG2) and 720 × 576 (DV) and a frame rate of 25 to 30 frames per second, a computational throughput of up to 1.8 billion operations per second (BOPS) is required. This is supported in the proposed architecture using a 40 MHz clock and an array of 40 to 45 parallel processors implemented in a 0.2 m CMOS technology and with a 1.5 V supply voltage. Power consumption is significantly reduced through the single-chip integration of the CMOS photo sensors, the embedded DRAM technology, and the proposed pipelined parallel processors. The parallel processors consume approximately 45 mW of power resulting a power efficiency of 40 BOPS/W.     

JPEG2000并行阵列式小波滤波器的VLSI结构设计

提出一种基于提升算法实现JPEG2000编码系统中的二维离散小波变换(Discrete Wavelet Transform)的并行阵列式的VLSI结构设计方法.利用该方法所得结构由两个行处理器,一个列处理器以及少量行缓存组成;行列处理器内部是由并行阵列式的处理单元组成;能使行和列滤波器同时进行滤波,用优化的移位加操作替代乘法操作.整个结构采用流水线的设计方法处理,在保证同样的精度下,大大减少了运算量和提高了硬件资源利用率,几乎达到100％,加快了变换速度,也减少了电路的规模.该结构对于N×N大小的图像,处理速度达到O(N²/2)个时钟周期.二维离散小波滤波器结构已经过FPGA验证,并可作为单独的IP核应用于正在开发的JPEG2000图像编解码芯片中.     

A contour-based approach to multisensor image registration

Image registration is concerned with the establishment of correspondence between images of the same scene. One challenging problem in this area is the registration of multispectral/multisensor images. In general, such images have different gray level characteristics, and simple techniques such as those based on area correlations cannot be applied directly. On the other hand, contours representing region boundaries are preserved in most cases. The authors present two contour-based methods which use region boundaries and other strong edges as matching primitives. The first contour matching algorithm is based on the chain-code correlation and other shape similarity criteria such as invariant moments. Closed contours and the salient segments along the open contours are matched separately. This method works well for image pairs in which the contour information is well preserved, such as the optical images from Landsat and Spot satellites. For the registration of the optical images with synthetic aperture radar (SAR) images, the authors propose an elastic contour matching scheme based on the active contour model. Using the contours from the optical image as the initial condition, accurate contour locations in the SAR image are obtained by applying the active contour model. Both contour matching methods are automatic and computationally quite efficient. Experimental results with various kinds of image data have verified the robustness of the algorithms, which have outperformed manual registration in terms of root mean square error at the control points.     

Hybrid image segmentation using watersheds and fast region merging

A hybrid multidimensional image segmentation algorithm is proposed, which combines edge and region-based techniques through the morphological algorithm of watersheds. An edge-preserving statistical noise reduction approach is used as a preprocessing stage in order to compute an accurate estimate of the image gradient. Then, an initial partitioning of the image into primitive regions is produced by applying the watershed transform on the image gradient magnitude. This initial segmentation is the input to a computationally efficient hierarchical (bottom-up) region merging process that produces the final segmentation. The latter process uses the region adjacency graph (RAG) representation of the image regions. At each step, the most similar pair of regions is determined (minimum cost RAG edge), the regions are merged and the RAG is updated. Traditionally, the above is implemented by storing all RAG edges in a priority queue. We propose a significantly faster algorithm, which additionally maintains the so-called nearest neighbor graph, due to which the priority queue size and processing time are drastically reduced. The final segmentation provides, due to the RAG, one-pixel wide, closed, and accurately localized contours/surfaces. Experimental results obtained with two-dimensional/three-dimensional (2-D/3-D) magnetic resonance images are presented.     

Parallel architectures for digital optical cellular imageprocessing

A parallel digital optical cellular image processor (DOCIP) functionally comprises an array of identical I-bit processing elements or cells, a fixed interconnection network, and a control unit. Four interconnection network topologies are described, and include two variants of a mesh-connected array and two variants of a cellular hypercube network. The instruction sets of these single-instruction multiple-data (SIMD) machines are based on a mathematical morphological theory, binary image algebra (BIA), which provide an inherently parallel programming structure for their control. Physically, a DOCIP architecture uses a holographic optical element in a 3D free-space optical system to implement off-chip interconnections, and an optoelectronic spatial light modulator to implement a 2D array of nonlinear processing elements and (optionally) local on-chip interconnections. Two examples are given. The first, an experimental implementation of a single 54-gate cell of the DOCIP, uses an optically recorded hologram for within-cell optical interconnections, and a spatial light modulator for a 2D array of optically accessible gates. The second, a design for an efficient and more manufacturable architecture, uses a computer-generated diffractive optical element for cell-to-cell interconnections, and a 20 smart-pixel array of DOCIP cells, each cell having electronic logic and optical input/output