数字电视机顶盒闪存文件系统

提出了数字电视机顶盒上的闪存文件系统,使用闪存作为存储介质,存储机顶盒中各种变化的数据.该系统使用均匀磨损、垃圾回收、断电保护等技术,提高了机顶金中数据的存储速度,延长了闪存的寿命,增强了机顶盒的稳定性.     

Memory on the move

The author describes how, competing for the US $ 11 billion portable electronic device memory market are several venerable but revitalized memory systems as well as new storage technologies: flash memory cards; PC memory cards; and small disk drives. Flashers, a relatively young technology contain one or more nonvolatile solid-state memory chips. They have no moving parts and retain data in the absence of power. Like these, but an industry unto itself, is the PC Card; now almost 10 years old, the business-card-sized memory and application device is heavily used to add functions to mobile computers. The spinners are a completely upgraded group of rotating disk drive systems based on both magnetic and optical technologies     

Java虚拟机内存管理分析

讨论了Java关键技术组成，深入介绍了Java虚拟机的体系结构，分析了虚拟机中内存管理的垃圾回收机制。同时，对现有的一些流行垃圾回收算法进行了深入分析和对比以及对某些算法的改进。Java虚拟机中存在多种垃圾回收机制，通过对Java虚拟机中内存管理机制的深入分析，可以使开发者针对不同的内存分配及回收策略选择合适的虚拟机。     

Energy-Efficient Streaming Using Non-volatile Memory

The disk and the DRAM in a typical mobile system consume a significant fraction (up to 30%) of the total system energy. To save on storage energy, the DRAM should be small and the disk should be spun down for long periods of time. We show that this can be achieved for predominantly streaming workloads by connecting the disk to the DRAM via a large non-volatile memory (NVM). We refer to this as the NVM-based architecture (NVMBA); the conventional architecture with only a DRAM and a disk is referred to as DRAMBA. The NVM in the NVMBA acts as a traffic reshaper from the disk to the DRAM. The total system costs are balanced, since the cost increase due to adding the NVM is compensated by the decrease in DRAM cost. We analyze the energy saving of NVMBA, with NAND flash memory serving as NVM, relative to DRAMBA with respect to (1) the streaming demand, (2) the disk form factor, (3) the best-effort provision, and (4) the stream location on the disk. We present a worst-case analysis of the reliability of the disk drive and the flash memory, and show that a small flash capacity is sufficient to operate the system over a year at negligible cost. Disk lifetime is superior to flash, so that is of no concern.     

Lazy-split B+-tree: a novel B+-tree index scheme for flash-based database systems

Flash memory is rapidly being deployed as a data storage medium for embedded systems and tablet computers due to its shock resistance, fast access, and low power consumption, etc. However, it has some intractable characteristics, such as erase-before-write, asymmetric read/write/erase speed, and a limited number of write/erase cycles. Due to these hardware limitations, magnetic disk-based systems and applications can hardly make full use of the advantages of flash memory when adopting it directly for storage. For example, the frequent changes of B-tree can degrade the performance and negatively influence the lifespan of flash memory. Most state-of-the-art studies on flash-aware index design focused mainly on buffer and storage mechanisms whereby they can obtain efficient I/Os to flash memory. In this paper, we identify the problems inherent in the related studies, and then introduce the concepts of lazy-split, modify-two-node, and semi-clean, which make possible the construction of a novel index solution, the Lazy-Split B⁺-tree (LSB⁺-tree). In detail, by their introduction, the first concept of LSB⁺-tree can efficiently reduce the number of node splits, the second can reduce the number of node modifications, and the last can make a further improvement on buffer space utilization and flash writes reduction.     

基于单片机的大容量静态存储器接口设计

为解决采集系统中大量数据存储及数据传输问题,对数据采集系统中基于单片机大容量静态存储器的应用进行了刨析。闪速存储器采用Atmel公司的AT29C040,对系统的总体设计思想及闪速存储器的特点做了阐述。给出了基于8位单片机进行4Mb高速存储器扩展的具体接口电路及其驱动程序。该系统具有在掉电情况下保存数据的功能,且具有存储数据容量大,体积小,功耗低,数据保存安全可靠等特点,适合于便携式流动性环境下的数据采集系统。     

快闪存储器──存储器家族的新成员

磁盘和快闪存储器有一个共同的特点，即整块数据存储。计算机通常采用磁盘存储整块数据，而快闪存储器在数据存储方面更具有优越性。我们研究了快闪存储单元及其工作原理，从中了解到快闪存储器的特性以及与便携式计算机比较的结果。     

基于NAND闪存的高性能和可靠的PRAID-6

基于固态硬盘的RAID-6阵列,在每次数据更新时,都需要计算和写入校验信息,降低了阵列的性能和缩短了固态硬盘的使用寿命,该论文提出了一种基于延迟写入校验信息策略的RAID-6,称为PRAID-6.在每次数据更新时,PRAID-6只计算部分校验信息,写入非易失性存储器P-Cache.在垃圾回收时,将部分校验信息与原校验信息合并,产生新的校验信息,写入固态硬盘.通过实验测试结果表明PRAID-6的响应时间比RAID-6减少了30%,比RAID-5减少了10%.垃圾回收开销比RAID-6减少了20%,比RAID-5减少了15%.     

Memory Power Reduction for High-Speed Implementation of Turbo Codes

Turbo codes achieve one of the highest coding gains known and should be the best candidates for error correction in high-speed communication systems. However, the standard implementation of their decoding algorithm suffers from a large latency and high power consumption making them improper for mobile interactive systems. To overcome this drawback, we carefully analyzed the Maximum A Posteriori algorithm, the key-building block of the decoder, and stated that memory accesses are the bottleneck. Therefore, we have systematically optimized the data transfer and storage. This paper presents the main results of this optimization, especially those concerning the memory organization and architecture.Both for the input and the metrics values, a memory sub-layer is introduced such that temporal data locality can be maximally exploited. The architecture is defined to optimally allocate memory units and assign arrays, such that the number of accesses is drastically reduced. The combined optimizations reduce the latency by a factor 600 and the energy per bit by a factor 20, breaking definitely an important obstruction to the application of turbo codes in high-speed communication systems.     

基于闪存的大容量存储阵列

大容量、高速度、高密度、低功耗、低成本、高可靠性和灵活性一直是星上记录设备信息存储技术的主要研究内容和追求目标。文中研究并实现了一种基于NAND型Flash的高速大容量固态存储系统,成果为实际研制应用于星的基于闪存的大容量存储器奠定了基础,具体较好的指导和借鉴意义。     

一种基于差分进化的Flash文件系统垃圾回收算法

垃圾回收算法对于Flash文件系统具有十分重要的意义.本文针对已有垃圾回收算法在存储容量剩余较小时垃圾回收性能急剧下降进而影响写入速率的问题,采用最优化方法,提出并实现了一种基于差分进化的垃圾回收算法.该算法能够使得垃圾回收的代价均匀化,在保证性能和损耗均衡的前提下,减少擦除次数,延长Flash寿命.实验结果验证了该算...     

用于视频监控的便携式数字录像机设计

针对各类视频监控和记录的应用特点和要求,设计并研制了一个基于嵌入式微处理器、专用视频压缩芯片及大容量IDE硬盘或电子盘的便携式数字录像机.讨论了系统结构设计及各功能模块的电路选择,介绍了关键接口电路设计和系统软件设计.系统采用单一直流电源供电,为了方便视频压缩数据的存取,设计了专用的文件系统.测试结果表明,系统性能良好、功能灵活,功耗低、集成度高、独立、便携,非常适合各类视频监控和记录应用.     

Embedded compact flash

A new data storage system designed for a data acquisition system is presented. The article describes the architecture of a large non-volatile memory data storage system (DSS) mainly developed for compact flash (CF) memory. A DSS handles the available storage space of the medium as a circular buffer rather than as an emulated disk in order to provide an efficient and easy to use software interface. A circular buffer is simply another name for a first-in-first-out (FIFO) buffer. The name circular buffer helps to visualize the wraparound condition. CF memories provide a persistent storage medium using solid-state memory technology at a lower cost and lower power consumption than other solid-state technologies.     

基于页面写相关的闪存转换层策略

针对固态硬盘(SSD)的闪存转换层(FTL)策略诸如BAST、FAST增加了垃圾回收的成本,带来了固态硬盘性能的下降等缺点,提出了一种基于页面“写相关”的FTL策略PWRST。PWRST的基本思想是分析I/O请求的访问历史并找出“写相关”的页面,将“写相关”的页面存储到同一数据块。从而减少垃圾回收开销和I/O请求的平均响应时间。实验结果表明PWRST在Postmark和IOzone负载下的响应时间比BAST减少了35%,比FAST减少了26%。在TPC-C负载下的响应时间比BAST减少了12%,比FAST减少了10%。     

Anticipatory I/O Management for Clustered Flash Translation Layer in NAND Flash Memory

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two‐level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two‐level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well‐known NAND FTL (NFTL) and adaptive FTL (AFTL).     

nand Flash Memory and Its Role in Storage Architectures

This papers reviews the increasing role of nand flash memory in storage architectures. nand flash has enjoyed a phenomenal growth rate in storage capacities as well as a steady decline in pricing during the past few years. These developments have enabled nand to enter and possibly change or displace some traditional storage architectures. However, besides cost, nand flash memory has some reliability and performance issues that will slow its adoption into all storage architectures. This paper will analyze the advantages and disadvantages of this technology and the implications to the current and possible future storage architectures. Moreover, we will analyze nand flash future density and costs trends and compare them with the traditional hard disk drive.      

3D NAND闪存数据保持力与初始状态依赖性研究

数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考.     

Fast NAND Flash Memory System for Instruction Code Execution

The objective of this research is to design a high‐performance NAND flash memory system containing a buffer system. The proposed instruction buffer in the NAND flash memory consists of two parts, that is, a fully associative temporal buffer for temporal locality and a fully associative spatial buffer for spatial locality. A spatial buffer with a large fetching size turns out to be effective for serial instructions, and a temporal buffer with a small fetching size is devised for branch instructions. Simulation shows that the average memory access time of the proposed system is better than that of other buffer systems with four times more space. The average miss ratio is improved by about 70% compared with that of other buffer systems.     

Physical Memory Collection and Analysis in Smart Grid Embedded System

Unlike the existing electric grid, the smart grid has a variety of functions that enable electric utility suppliers and consumers to perform dual exchanges of real-time information by adding IT technology. Therefore, the systems of smart grid suppliers and those of users are always connected through a network, which means that the systems related to the smart grid could become targets of malicious attackers. The various smart grid systems could have different hardware configuration from those of general systems, but their fundamental operating mechanism is the same as that of the general computer system. When a system is operating, its information and the data used by a program are loaded into the system’s memory. In this paper, we studied the method of physical memory collection and analysis in smart grid embedded systems in order to help investigate crimes related to smart grids. In addition, we verify the method studied in this paper through the collection and analysis of physical memory in the virtual Linux environment using a virtual machine.     

Power-Aware Data Management Based on Hybrid RAM-NVM Memory for Smart Bracelet

Wearable devices become popular because they can help people observe health condition. The battery life is the critical problem for wearable devices. The non-volatile memory (NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption, NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory (DRAM). In this paper, we assume to use hybrid random access memory (RAM) and NVM architecture for the smart bracelet system. This paper presents a data management algorithm named bracelet power-aware data management (BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.